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mt9d015: 1/5-inch 2 mp cmos digital image sensor features mt9d015_ds rev. m pub. 4/15 en 1 ?semiconductor components industries, llc,2015 1/5-inch 2 mp cmos digital image sensor mt9d015 datasheet, rev. m for the latest datasheet, please visit www.onsemi.com features ? superior low light performance ? high sensitivity ?low dark current ? simple two-wire serial interface ? auto black level calibration ? programmable controls: gain, frame size/rate, exposure, left?right and top?bottom image reversal, window size and panning ? data interface: ccp2 compliant sub-low-voltage differential signaling (sub-lvds) or single lane serial mobile industry processor interface (mipi) ? smia 1.0 compatible; mipi 1.0 compliant ? on-chip phase-locked loop (pll) oscillator ? bayer-pattern down-size scaler ? integrated lens shading correction ? internal power switch for ultra-low standby current consumption ? 30 fps at full resolution ? 2d defect pixel correction ? 2624-bit one-time programmable memory (otpm) for storing module information and lens shading correction. general description the on semiconductor mt9d015 is a 1/5-inch uxga-format cmos active-pixel digital image sensor with a pixel array of 1600h x 1200v (1608h x 1208v including border pixels). it incorpo- rates sophisticated on-chip camera functions such as windowing, mirroring, column and subsampling modes. it is programmable through a simple two-wire serial interface and has very low power consumption. applications ? cellular phones ? digital still cameras ?pc cameras ?pdas table 1: key performance parameters parameter value die size 4356.15 ? m (h) x 4354.85 ? m (v) optical format 1/5-inch uxga (4:3) active imager size 2.828 mm (h) x 2.128 (v) active pixels 1608 h x 1208 v pixel size 1.75 x 1.75 ? m color filter array rgb bayer pattern shutter type electronic rolling shutter (ers) input clock frequency 6C27 mhz maximum data rate 640 mb/s (ccp) and 768 mb/s (mipi) ccp frame rate uxga (1600 x 1200) programmable up to 21 fps in profile 0 mode (raw10) programmable up to 30 fps in profile 1/2 mode (raw10) xga (1024 x 768) programmable up to 42 fps in profile 0 mode (raw10) programmable up to 61 fps in profile 1/2 mode (raw10) hd (1280 x 720) 30 fps mipi frame rate uxga (1600 x 1200) 30 fps (raw10) vga (640 x 480) 60 fps (raw10) qvga (320x240) 120 fps (raw10) hd (1280 x 720) 30 fps (raw10) adc resolution 10-bit responsivity 0.86 v/lux-sec dynamic range 62 db snr max 38.7 db supply voltage analog 2.40C2.90 v (2.80 v nominal) digital 1.70C1.90 v (1.80 v nominal) power consumption 272 mw at 30 fps (typ) operating temperature C30c to +70c packaging bare die
mt9d015_ds rev. m pub. 4/15 en 2 ?semiconductor components industries, llc,2015. mt9d015: 1/5-inch 2 mp cmos digital image sensor ordering information ordering information table 2: available part numbers part number product description orderable product attribute description mt9d015d00stcmc25bc1-200 2 mp 1/4" cis die sales, 200 ? m thickness MT9D015D00STCPC25BC1-400 2 mp 1/4" cis die sales, 400 ? m thickness
mt9d015_ds rev. m pub. 4/15 en 3 ?semiconductor components industries, llc,2015. mt9d015: 1/5-inch 2 mp cmos digital image sensor table of contents table of contents general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 ordering information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 functional overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 operating modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 two-wire serial register interf ace . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 embedded data format and control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 programming restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 control of the signal interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 clocking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 sensor core digital data path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 digital data path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 timing specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 electrical specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 chief ray angle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72 smia and mipi specification reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
mt9d015_ds rev. m pub. 4/15 en 4 ?semiconductor components industries, llc,2015. mt9d015: 1/5-inch 2 mp cmos digital image sensor list of figures list of figures figure 1: block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 figure 2: pixel color pattern detail (top ri ght corner) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 figure 3: typical configuration (connection) ? serial output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 figure 4: typical configuration (connection) ? mipi mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 figure 5: single read from random location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 figure 6: single read from current locati on. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 figure 7: sequential read, start from rand om location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 figure 8: sequential read, start from curre nt location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 figure 9: single write to random location. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 figure 10: sequential write, start at rand om location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 figure 11: effect of limiter on the smia da ta path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 figure 12: timing of smia data path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 figure 13: mt9d015 system states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 figure 14: mt9d015 smia profile 1/ 2 clocking structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 figure 15: mt9d015 smia profile 0 clocking structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 figure 17: full resolution frame structure example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 figure 18: effect of horizontal_mirror on readout order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 figure 19: effect of vertic al_flip on readout order. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 figure 20: effect of x_odd_inc = 3 on readout sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 figure 21: pixel readout (no subsampling). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 figure 22: pixel readout (x_odd_inc = 3, y_o dd_inc = 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 figure 23: 100 percent color bars test pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 figure 24: fade-to-gray color bars test pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 figure 25: test cursor behavior when imag e_orientation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 figure 26: data path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 figure 27: power-up sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 figure 28: power-down sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 figure 29: soft standby and soft reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 figure 30: definition of timing for two-wi re serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 figure 31: internal power-on reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 figure 32: chief ray angle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
mt9d015_ds rev. m pub. 4/15 en 5 ?semiconductor components industries, llc,2015. mt9d015: 1/5-inch 2 mp cmos digital image sensor list of tables list of tables table 1: key performance parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 table 2: available part numbers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 table 3: signal descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 table 4: address space regions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 table 5: data formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 table 6: embedded data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 table 7: definitions for programming rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 table 8: programming rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 table 9: pll in system states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 table 10: signal state during reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 table 11: streaming/standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 table 12: row address sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 table 13: minimum row time and blanking numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 table 14: minimum frame time and blanking numbers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 table 15: fine_integration_time limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 table 16: gain table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 table 17: test patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 table 18: power-up sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 table 19: power-down sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 table 20: electrical characterist ics (extclk) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 table 21: two-wire serial interface electric al characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 table 22: two-wire serial interfac e timing specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 table 23: electrical characteristics (serial ccp2 pixel data inte rface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 table 24: electrical characteristics (serial mipi pixel data inte rface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 table 25: electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 table 26: power-on reset characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 table 27: dc electrical definitions and char acteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 table 28: absolute maximum values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
mt9d015_ds rev. m pub. 4/15 en 6 ?semiconductor components industries, llc,2015. mt9d015: 1/5-inch 2 mp cmos digital image sensor general description general description the mt9d015 digital image sensor features on semiconductor?s breakthrough low noise cmos imaging technology that achi eves near-ccd image quality (based on signal-to-noise ratio and low-light sensitivity) while maintaining the inherent size, cost, and integration advantages of cmos. when operated in its default mode, the sensor generates a uxga image at 21 frames per second (fps) when ext_clk_freq_mhz = 16 mh z. an on-chip analog-to-digital converter (adc) generates a 10-bit value for each pixel. functional overview the mt9d015 is a progressive-scan sensor th at generates a stream of pixel data at a constant frame rate. it uses an on-chip, phas e-locked loop (pll) to generate all internal clocks from a single master input clock running between 6 and 27 mhz. the maximum pixel rate is 64 mp/s, corresponding to a vi deo timing pixel clock rate of 91.4 mhz. a block diagram of the sensor is shown in figure 1. figure 1: block diagram the core of the sensor is a 2mp active-pix el array. the timing and control circuitry sequences through the rows of the array, rese tting and then reading each row in turn. in the time interval between resetting a row and re ading that row, the pixels in the row inte- grate incident light. the exposure is controlled by varying the time interval between reset and readout. once a row has been read, the data from the columns is sequenced through an analog signal chai n (providing offset correction and gain), and then through an adc. the output from the adc is a 10-bit value for each pixel in the array. the adc output passes through a digital processing signal chain (which provides further data corrections and applies digital gain). the pixel array contains optically active and light-shielded (dark) pixels. the dark pixels are used to provide data for on-chip offset-correction algorithms (black level control). the sensor contains a set of control and status registers that can be used to control many aspects of the sensor behavior including the frame size, exposure, and gain setting. these registers can be accessed through a two-wire serial interface. active-pixel sensor (aps) array analog processing adc scaler limiter shading correction fifo timing control control registers data out two-wire serial interface sync signals
mt9d015_ds rev. m pub. 4/15 en 7 ?semiconductor components industries, llc,2015. mt9d015: 1/5-inch 2 mp cmos digital image sensor functional overview the output from the sensor is a bayer pattern ; alternate rows are a sequence of either green and red pixels or blue and green pixels. the offset and gain stages of the analog signal chain provide per-color control of the pixel data. the control registers, timing and control, and digital processing functions shown in figure 1 on page 6 are partitioned into three logical parts: ? a sensor core that provides arra y control and data path corrections. ? a digital shading correction block to comp ensate for color/brightness shading intro- duced by the lens or cra curve mismatch. ? functionality to support the smia standard . this includes a horizontal and vertical image scaler, a limiter, a data compress or, an output fifo, and a serializer. the output fifo prevents data bursts by keeping the data rate continuous. pixel array the sensor core uses a bayer color pattern, as shown in figure 2. the even-numbered rows contain green and red pixels; odd-numbered rows contain blue and green pixels. even-numbered columns contain green and blue pixels; odd-numbered columns contain red and green pixels. figure 2: pixel color pattern detail (top right corner) black pixels column readout direction . . . ... row readout direction gr b gr b r gb r gb gr b gr b r gb r gb gr b gr b first clear pixel
mt9d015_ds rev. m pub. 4/15 en 8 ?semiconductor components industries, llc,2015. mt9d015: 1/5-inch 2 mp cmos digital image sensor operating modes operating modes the mt9d015 can operate in either serial ccp2 or serial mipi mode (preconfigured at the factory). in both cases, the sensor has a smia-compatible register interface while the i 2 c device address is compliant with smia or mipi requirements as appropriate. the reset level on the test pin must be tied in a way that is compatible with the configured serial interface of the sensor, for instance test = 0 for ccp2 and test = 1 for mipi. typical configurations are shown in figure 3 and figure 4 on page 9. these operating modes are described in ?control of the signal interface? on page 32. for low-noise operation, the mt9d015 requires separate power supplies for analog and digital. incoming digital and analog ground co nductors can be tied together next to the die. both power supply rails should be decoupled from ground using capacitors as close as possible to the die. the use of inductance filters is not recommended on the power supplies or output signals. figure 3: typical configuration (connection) C serial output mode notes: 1. all power supplies mu st be adequately decoupled. 2. a resistor value of 1.5k ?? is recommended, but it may be greater for slower two-wire speed. 3. test must be tied to gnd for smia configuration. 4. also referred to as reset_bar. 5. the gpi pins can be statically pulled high or low and used as module ids. all gpi pins must be driven to avoid leakage current. 6. on semiconductor recommends that 0.1 ? f and 1 ? f decoupling capacitors for each power supply are mounted as close as possible to the pad. actu al values and results may vary depending on lay- out and design considerations. v dd v dd _pll v aa _pix s data s clk xshutdown 4 extclk d gnd v aa two- wire serial interface to controller gpi[3:0] 5 atest1 atest2 test 3 active low reset digital power 6 analog power 6 r pull-up external clock in (6C27 mhz) general purpose inputs no connect no connect x x data_n data_p clk_n clk_p a gnd analog power 1 digital power 1 1.5k 2 1.5k 2
mt9d015_ds rev. m pub. 4/15 en 9 ?semiconductor components industries, llc,2015. mt9d015: 1/5-inch 2 mp cmos digital image sensor operating modes 7. v pp , which can be used during the module manufacturi ng process, is not shown in figure 3. this pad is left unconnected during normal operation. 8. atest1 and atest2 must be floating. figure 4: typical configuration (connection) C mipi mode notes: 1. all power supplies mu st be adequately decoupled. 2. a resistor value of 1.5k ?? is recommended, but it may be greater for slower two-wire speed. 3. test must be tied to v dd for mipi configuration. 4. also referred to as reset_bar. 5. the gpi pins can be statically pulled high or low and used as module ids. all gpi pins must be driven to avoid leakage current. 6. on semiconductor recommends that 0.1 ? f and 1 ? f decoupling capacitors for each power supply are mounted as close as possible to the pad. actu al values and results may vary depending on lay- out and design considerations. 7. v pp , which can be used during the module manufacturi ng process, is not shown in figure 3. this pad is left unconnected during normal operation. 8. atest1 and atest2 must be floating. v dd v dd _pll v aa _pix s data s clk xshutdown 4 extclk d gnd v aa two- wire serial interface to controller gpi[3:0] 5 atest1 atest2 test 3 active low reset digital power 6 analog power 6 r pull-up external clock in (6C27 mhz) general purpose inputs no connect no connect x x data_n data_p clk_n clk_p a gnd analog power 1 digital power 1 1.5k 2 1.5k 2
mt9d015_ds rev. m pub. 4/15 en 10 ?semiconductor components industries, llc,2015. mt9d015: 1/5-inch 2 mp cmos digital image sensor signal descriptions signal descriptions table 3 provides signal descriptions for mt9d015 die. for pad location and aperture information, refer to the mt9d015 die data sheet. table 3: signal descriptions pad name pad type description extclk input master clock input. pll input clock. 6C27 mhz. reset_bar (xshutdown) input asynchronous active low reset. when asserted, data output stops and all internal registers are restored to their factory default settings. s clk input serial clock for access to control and status registers. gpi[3:0] input genera l purpose inputs. after reset, these pads are powered up (ena bledsee r0x301a) by default; these pads must be bonded to a high or low state. failure to bond as required will re sult in excessive power consumption. test input enable manufacturing test modes. co nnect to dgnd for normal operation of the ccp2-configured sensor, or connect to vd d power for the mipi configured sensor. s data i/o serial data for reads from and writes to control and status registers. data_p output differential ccp2/mipi (s ub-lvds) serial data (positive). data_n output differential ccp2/mipi (sub-lvds) serial data (negative). clk_p output differential ccp2/mipi (sub-l vds) serial clock/strobe (positive). clk_n output differential ccp2/mipi (sub-l vds) serial clock/strobe (negative). v aa supply analog power supply. v dd _pll supply pll power supply. v aa _pix supply analog power supply. a gnd supply analog ground. v dd supply digital power supply. d gnd supply digital ground. v pp supply otpm programming power supply
mt9d015_ds rev. m pub. 4/15 en 11 ?semiconductor components industries, llc,2015. mt9d015: 1/5-inch 2 mp cmos digital image sensor two-wire serial register interface two-wire serial register interface the two-wire serial interface bus enables read /write access to control and status regis- ters within the sensor. this interface is design ed to be compatible with the smia 1.0 part 2: ccp2 specification camera control interfac e (cci), which uses the electrical charac- teristics and transfer protocols of the i 2 c specification. the protocols described in the i 2 c specification allow the slave device to drive s clk low; the sensor uses s clk as an input only and therefore never drives it low. protocol data transfers on the two-wire serial inte rface bus are performed by a sequence of low-level protocol elements: 1. a (repeated) start condition 2. a slave address/data direction byte 3. an (a no) acknowledge bit 4. a message byte 5. a stop condition the bus is idle when both s clk and s data are high. control of the bus is initiated with a start condition, and the bus is released wi th a stop condition. only the master can generate the start and stop conditions. start condition a start condition is defined as a high-to-low transition on s data while s clk is high. at the end of a transfer, the master can generate a start condition without previously generating a stop cond ition; this is known as a ?repeated start? or ?restart? condition. slave address/data direction byte bits [7:1] of this byte represent the device slave address and bit [0] indicates the data transfer direction. a ?0? in bit [0] indicates a write, and a ?1? indicates a read. the default slave addresses used by the mt9d015 for the mipi configured sensor are 0x6c (write address) and 0x6d (read address) in accordan ce with the mipi specification. but for the ccp2 configured sensor, the default slave addresses used are 0x20 (write address) and 0x21 (read address) in accordan ce with the smia specification. acknowledge bit each 8-bit data transfer is followed by an acknowledge bit or a no-acknowledge bit in the s clk clock period following the data transfer. the transmitter (which is the master when writing, or the slave when reading) releases s data . the receiver indicates an acknowl- edge bit by driving s data low. as for data transfers, s data can change when s clk is low and must be stable while s clk is high. no-acknowledge bit the no-acknowledge bit is generated when the receiver does not drive s data low during the s clk clock period following a data transf er. a no-acknowledge bit is used to terminate a read sequence. message byte message bytes are used for sending register addresses and register write data to the slave device and for retrieving register read data. the protocol used is outside the scope of the smia cci.
mt9d015_ds rev. m pub. 4/15 en 12 ?semiconductor components industries, llc,2015. mt9d015: 1/5-inch 2 mp cmos digital image sensor two-wire serial register interface stop condition a stop condition is defined as a low-to-high transition on s data while s clk is high. data transfer data is transferred serially, 8 bits at a time, with the msb transmitted first. each byte of data is followed by an acknowledge bit or a no-acknowledge bit. this data transfer mechanism is used for the slave address/da ta direction byte and for message bytes. one data bit is transferred during each s clk clock period. s data can change when s clk is low and must be stable while s clk is high. typical sequence a typical read or write sequence begins by the master generating a start condition on the bus. after the start condition, the master sends the 8-bit slave address/data direction byte. the last bit indicates whether the request is for a read or a write, where a ?0? indicates a write and a ?1? indicates a read. if the address matches the address of the slave device, the slave device acknowledges receipt of the address by generating an acknowledge bit on the bus. if the request was a read, the master sends the 8-bit write slave address/data direction byte and 16-bit register address, just as in the write request. the master then generates a (re)start condition and the 8-bit read slave address/data direction byte, and clocks out the register data, 8 bits at a time. the mast er generates an acknowledge bit after each 8-bit transfer. the slave?s internal register address is automatically incremented after every 8 bits are transferred. the data transfer is stopped when the master sends a no-acknowledge bit.
mt9d015_ds rev. m pub. 4/15 en 13 ?semiconductor components industries, llc,2015. mt9d015: 1/5-inch 2 mp cmos digital image sensor two-wire serial register interface single read from random location this sequence (figure 5) starts with a dummy write to the 16-bit address that is to be used for the read. the master terminates th e write by generating a restart condition. the master then sends the 8-bit read slave address/data direction byte and clocks out 1 byte of register data. the master terminates the read by generating a no-acknowledge bit followed by a stop condition. figure 5 sh ows how the internal register address main- tained by the mt9d015 is loaded and incremented as the sequence proceeds. figure 5: single read from random location single read from current location this sequence (figure 6) performs a read using the current value of the mt9d015 internal register address. the master terminates the read by generating a no-acknowl- edge bit followed by a stop condition. the figure shows two independent read sequences. figure 6: single read from current location sequential read, start from random location this sequence (figure 7) starts in the same way as the single read from random loca- tion (figure 5). instead of generating a no-ackno wledge bit after the first byte of data has been transferred, the master generates an acknowledge bit and continues to perform byte reads until l by tes have been read. figure 7: sequential read, start from random location s = start condition p = stop condition sr = restart condition a = acknowledge a = no-acknowledge slave to master master to slave slave address 0 s a reg address[15:8] a reg address[7:0] slave address a a 1 sr read data p previous reg address, n reg address, m m+1 a slave address 1 s a read data slave address a 1 s p read data p previous reg address, n reg address, n+1 n+2 a a slave address 0 s sr a reg address[15:8] read data read data a reg address[7:0] a read data slave address previous reg address, n reg address, m m+1 m+2 m+1 m+3 a 1 read data read data m+l-2 m+l-1 m+l a p aa a a
mt9d015_ds rev. m pub. 4/15 en 14 ?semiconductor components industries, llc,2015. mt9d015: 1/5-inch 2 mp cmos digital image sensor two-wire serial register interface sequential read, start from current location this sequence (figure 8) starts in the same wa y as the single read from current location (figure 6 on page 13). instead of generating a no-acknowledge bit after the first byte of data has been transferred, the master gene rates an acknowledge bit and continues to perform byte reads until l bytes have been read. figure 8: sequential read, start from current location single write to random location this sequence (figure 9) begins with the mast er generating a start condition. the slave address/data direction byte signals a writ e and is followed by the high then low bytes of the register address that is to be writ ten. the master follows this with the byte of write data. the write is terminated by the master generating a stop condition. figure 9: single write to random location sequential write, start at random location this sequence (figure 10) starts in the same way as the single write to random location (figure 9). instead of generating a stop cond ition after the first byte of data has been transferred, the master continue s to perform byte writes until l bytes have been written. the write is terminated by the ma ster generating a stop condition. figure 10: sequential write, start at random location read data read data previous reg address, n n+1 n+2 n+l-1 n+l read data slave address a 1 read data a p s a a a slave address 0 s a reg address[15:8] a a reg address[7:0] a previous reg address, n reg address, m m+1 m+2 m+1 m+3 a a a m+l-2 m+l-1 m+l a a p write data write data write data write data write data slave address 0 s a reg address[15:8] a a reg address[7:0] a previous reg address, n reg address, m m+1 m+2 m+1 m+3 a a a m+l-2 m+l-1 m+l a a p write data write data write data write data write data
mt9d015_ds rev. m pub. 4/15 en 15 ?semiconductor components industries, llc,2015. mt9d015: 1/5-inch 2 mp cmos digital image sensor registers registers note: the detailed register lists and descriptions are in a separate document, the mt9d015 register reference. the mt9d015 provides a 32-bit register address space accessed through a serial inter- face (?single read from random location? on page 13). each register location is 8 or 16 bits in size. the address space is divided into the five major regions shown in table 4. register notation the underlying mechanism for reading and wr iting registers provides byte write capa- bility. however, it is convenient to consider some registers as multiple adjacent bytes. the mt9d015 uses 8-bit, 16-bit, and 32-bit re gisters, all implemented as 1 or more bytes at naturally aligned, contiguous locations in the address space. in this document, registers are described either by address or by name. when registers are described by address, the size of the regi sters is explicit. for example, r0x3024 is an 8-bit register at address 0x3024, and r0x3000 ? 1 is a 16-bit register at address 0x3000? 0x3001. when registers are described by name, refer to the register table to determine their size. register aliases a consequence of the internal architecture of the mt9d015 is that some registers are decoded at multiple addresses. some registers in ?configuration space? are also decoded in ?manufacturer-specific space.? to provide unique names for all registers, the name of the register within manufacturer-specific register space has a trailing underscore. for example, r0x0000 ? 1 is model_id, and r0x3000 ? 1 is model_id_ (see the register table for more examples). the effect of reading or writ ing a register through any of its aliases is identical. bit fields some registers provide control of several differe nt pieces of related functionality, making it necessary to refer to bit fields within regist ers. as an example of the notation used for this, the least significant 4 bits of the model_id register are referred to as model_id[3:0] or r0x0000 ? 1[3:0]. table 4: address space regions address range description 0x0000C0x0fff configuration registers (read-only and read-write dynamic registers) 0x1000C0x1fff parameter limit registers (read-only static registers) 0x2000C0x2fff image statistics registers (none currently defined) 0x3000C0x3fff manufacturer-specific registers (read-only and read-write dynamic registers) 0x4000C0xffff reserved (undefined)
mt9d015_ds rev. m pub. 4/15 en 16 ?semiconductor components industries, llc,2015. mt9d015: 1/5-inch 2 mp cmos digital image sensor registers bit field aliases in addition to the register aliases descri bed in ?register aliases? on page 15, some register fields are aliased in multiple places. for example, r0x0100 (mode_select) has only one operational bit, r0x0100[0]. this bi t is aliased to r0x301a?b[2]. the effect of reading or writing a bit field through any of its aliases is identical. byte ordering registers that occupy more than 1 byte of address space are shown with the lowest address in the highest-order byte lane to ma tch the byte-ordering on the smia bus. for example, the model_id register is r0x0000 ? 1. in the register table the default value is shown as 0x1501. this means that a read from address 0x0000 would return 0x15, and a read from address 0x0001 would return 0x01. when reading this register as two 8-bit transfers on the serial interface, the 0x15 will appear on the serial interface first, followed by the 0x01. address alignment all register addresses are aligned naturally. re gisters that occupy 2 bytes of address space are aligned to even 16-bit addresses, and registers that occupy 4 bytes of address space are aligned to 16-bit addresses th at are an integer multiple of 4. bit representation for clarity, 32-bit hex numbers are shown wi th an underscore between the upper and lower 16 bits. for example: 0x3000_01ab. data format most registers represent an unsigned binary value or set of bit fields. for all other register formats, the format is stated explicitly at th e start of the register description. the nota- tion for these formats is shown in table 5. table 5: data formats name description fix16 signed fixed-point, 16-bit number: twos complement number, 8 fractional bits. examples: 0x0100 = 1.0, 0x8000 = C128, 0xffff = C0.0039065 ufix16 unsigned fixed-point, 16-bit number: 8.8 format. examples: 0x0100 = 1.0, 0x280 = 2.5 flp32 signed floating-point, 32-bit number: ieee 754 format. ex ample: 0x 4280_0000 = 64.0
mt9d015_ds rev. m pub. 4/15 en 17 ?semiconductor components industries, llc,2015. mt9d015: 1/5-inch 2 mp cmos digital image sensor registers register behavior registers vary from ?read-only,? ?read/write,? and ?read, write-1-to-clear.? double-buffered registers some sensor settings cannot be changed duri ng frame readout. for example, changing r0x0344?5 (x_addr_start) partway through frame readout would result in inconsistent row lengths within a frame. to avoid this, the mt9d015 double-bu ffers many registers by implementing a ?pending? and a ?live? version. reads and writes access the pending register. the live register controls the sensor operation. the value in the pending register is transferre d to a live register at a fixed point in the frame timing, called frame start. frame start is defined as the point at which the first dark row is read out internally to the sensor . in the register tables the ?sync?d? column shows which registers or register fields are double-buffered in this way. using grouped_parameter_hold register grouped_parameter_hold (r0x0104) ca n be used to inhibit transfers from the pending to the live registers. when the mt9d 015 is in streaming mode, write ?1? to this register before making changes to any group of registers where a set of changes is required to take effect simultaneously. when th is register is set to ?0,? all transfers from pending to live registers take place on the next frame start. an example of the consequences of failing to set this bit follows: ? an external auto exposure algorithm might want to change both gain and integra- tion time between two frames. if the next frame starts between these operations, it will have the new gain, but not the new integration time, which would return a frame with the wrong brightness that migh t lead to a feedback loop with the ae algorithm resulting in flickering. bad frames a bad frame is a frame where all rows do no t have the same integration time or where offsets to the pixel values have changed during the frame. many changes to the sensor register settings can cause a bad frame. for example, when line_length_pck (r0x0342?3) is changed, the new register value does not affect sensor behavior until the next frame start. however, the frame that would be read out at that frame start will have been integrated using th e old row width, so reading it out using the new row width would result in a frame with an incorrect integration time. in the register tables, the ?bad frame? column shows where changing a register or register field will cause a bad frame. the following notation is used: n?no. changing the register value will not produce a bad frame. y?yes. changing the register value might produce a bad frame. ym?yes; but the bad frame will be masked out when mask_corrupted_frames (r0x0105) is set to ?1.?
mt9d015_ds rev. m pub. 4/15 en 18 ?semiconductor components industries, llc,2015. mt9d015: 1/5-inch 2 mp cmos digital image sensor registers changes to integration time if the integration time is changed while frame_valid (fv) is asserted for frame n , the first frame output using the ne w integration time is frame (n + 2) . the sequence is as follows: 1. during frame n , the new integration time is held in the pending register. 2. at the start of frame ( n + 1 ), the new integration time is tr ansferred to the live register. integration for each row of frame ( n + 1 ) has been completed using the old integration time. 3. the earliest time that a row can start integrating using the new integration time is immediately after that row has been read for frame ( n + 1 ). the actual time that rows start integrating using the new integration time is dependent upon the new value of the integration time. 4. when frame ( n + 2 ) is read out, it will have been integrated using the new integration time. if the integration time is changed on successive frames, each value written will be applied for a single frame; the latency betwee n writing a value and it affecting the frame readout remains at two frames. changes to gain settings usually, when the gain settings are changed, the gain is updated on the next frame start. when the integration time and the gain are ch anged at the same time, the gain update is held off by one frame so that the first fram e output with the new integration time also has the new gain applied. in this case, a new gain should not be set during the extra frame delay. there is an option to turn off the extra frame delay by setting reset_reg- ister[14] bit. embedded data the current values of implemented registers in the address range 0x0000?0x0fff can be generated as part of the pixel data. this em bedded data is enabled by default when the serial pixel data interface is enabled. the current value of a register is the value that was used for the image data in that frame. in general, this is the live value of the register. the exceptions are: ? the integration time is delayed by one further frame, so that the value corresponds to the integration time used for the image data in the frame. see ?changes to integration time? on page 18. ? the pll timing registers are not double-buffered, because the result of changing them in streaming mode is undefined. therefore, the pending and live values for these registers are equivalent.
mt9d015: 1/5-inch 2 mp cmos digital image sensor embedded data format and control mt9d015_ds rev. m pub. 4/15 en 19 ?semiconductor components industries, llc,2015. embedded data format and control when the serial pixel data path is selected, the first two rows of the output image contain register values that are appropriate for the im age. in this mode, the first two lines and the last line of data are not equally spaced. the fo rmat of this data is shown in table 6. in the table, 8-bit (raw8) and 10-bit (raw10) versions of the data are shown. the 10-bit format places the data byte in bits [9:2] and sets bits [1:0] to a constant value of 01. register values that are shown as ???? are dynamic and may change from frame to frame. when the parallel pixel data path is select ed and r0x306e-f[2:0]= 2 (parallel pixel data output mux selects fifo data). the output image contains two rows of embedded data. table 6: embedded data row 0 row 1 offset 10-bit 8-bit two-wire serial interface address comment 10-bit 8-bit two- wire serial interface address comment 0 0x029 0x0a 2-byte tagged data format (embedded data) 0x029 0x0a 2-byte tagged data format (embedded data) 1 0x2a9 0xaa cci register index msb 0x2a9 0xaa cci register index msb 2 0x001 0x00 address 00xx 0x009 0x02 address 02xx 3 0x295 0xa5 cci register index lsb 0x295 0xa5 cci register index lsb 4 0x001 0x00 address xx00 0x001 0x00 address xx00 5 0x169 0x5a auto increment 0x169 0x5a auto increment 6 0x055 0x15 0 model_id hi ?? ?? 200 fine_integration_time hi 7 0x169 0x5a 0x169 0x5a 8 0x005 0x01 1 model_id lo ?? ?? 201 fine_integration_time lo 9 0x169 0x5a 0x169 0x5a 10 0x080 0x20 2 revision_number ?? ?? 202 coarse_integration_time hi 11 0x169 0x5a 0x169 0x5a 12 0x019 0x06 3 manufacturer_id ?? ?? 203 coarse_integration_time lo 13 0x169 0x5a 0x169 0x5a 14 0x029 0x0a 4 smia_version ?? ?? 204 analogue_gain_code_glob al hi 15 0x169 0x5a 0x169 0x5a 16 ?? ?? 5 frame_count ?? ?? 205 analogue_gain_code_glob al lo 17 0x169 0x5a 0x169 0x5a 18 ?? ?? 6 pixel_order ?? ?? 206 analogue_gain_code_gree nr hi 19 0x169 0x5a 0x169 0x5a 20 ?? ?? 7 reserved ?? ?? 207 analogue_gain_code_gree nr lo 21 0x169 0x5a 0x169 0x5a 22 0x001 0x00 8 data_pedestal_hi ?? ?? 208 analogue_gain_code_red hi 23 0x169 0x5a 0x169 0x5a
mt9d015: 1/5-inch 2 mp cmos digital image sensor embedded data format and control mt9d015_ds rev. m pub. 4/15 en 20 ?semiconductor components industries, llc,2015. 24 0x0a9 0x2a 9 data_pedestal lo ?? ?? 209 analogue_gain_code_red lo 25 0x2a9 0xaa cci register index msb 0x169 0x5a 26 0x001 0x00 address 00xx ?? ?? 020a analogue_gain_code_blue hi 27 0x295 0xa5 cci register index lsb 0x169 0x5a 28 0x041 0x10 address xx10 ?? ?? 020b analogue_gain_code_blue lo 29 0x169 0x5a auto increment 0x169 0x5a 30 0x005 0x01 10 revision_number_minor ?? ?? 020c analogue_gain_code_gree nb hi 31 0x169 0x5a 0x169 0x5a 32 0x001 0x00 11 smia_pp_version ?? ?? 020d analogue_gain_codegreen b lo 33 0x169 0x5a 0x169 0x5a 34 0x001 0x00 12 module_date_year ?? ?? 020e digital_gain_greenr hi 35 0x169 0x5a 0x169 0x5a 36 0x001 0x00 13 module_date_month ?? ?? 020f digital_gain_greenr lo 37 0x169 0x5a 0x169 0x5a 38 0x001 0x00 14 module_date_day ?? ?? 210 digital_gain_red hi 39 0x169 0x5a 0x169 0x5a 40 0x001 0x00 15 module_date_phase ?? ?? 211 digital_gain_red lo 41 0x169 0x5a 0x169 0x5a 42 0x001 0x00 16 sensor_model_id hi ?? ?? 212 digital_gain_blue hi 43 0x169 0x5a 0x169 0x5a 44 0x001 0x00 17 sensor_model_id lo ?? ?? 213 digital_gain_blue lo 45 0x169 0x5a 0x169 0x5a 46 0x005 0x01 18 sensor_revision_numb er ?? ?? 214 digital_gain_greenb hi 47 0x169 0x5a 0x169 0x5a 48 0x001 0x00 19 sensor_manufacturer_id ?? ?? 215 digital_gain_greenb lo 49 0x169 0x5a 0x2a9 0xaa cci register index msb 50 0x001 0x00 1a sensor_firmwave_ version 0x00d 0x03 address 03xx 51 0x169 0x5a 0x295 0xa5 cci register index lsb 52 ?? ?? 1b reserved 0x001 0x00 address xx00 53 0x169 0x5a 0x169 0x5a auto increment 54 0x001 0x00 1c serial_number_0 hi ?? ?? 300 vt_pix_clk_div hi 55 0x169 0x5a 0x169 0x5a 56 0x001 0x00 1d serial_number_0 lo ?? ?? 301 vt_pix_clk_div lo 57 0x169 0x5a 0x169 0x5a 58 0x001 0x00 1e serial_number_1 hi ?? ?? 302 vt_sys_clk_div hi table 6: embedded data row 0 row 1 offset 10-bit 8-bit two-wire serial interface address comment 10-bit 8-bit two- wire serial interface address comment
mt9d015: 1/5-inch 2 mp cmos digital image sensor embedded data format and control mt9d015_ds rev. m pub. 4/15 en 21 ?semiconductor components industries, llc,2015. 59 0x169 0x5a 0x169 0x5a 60 0x001 0x00 1f serial_number_1 lo ?? ?? 303 vt_sys_clk_div lo 61 0x2a9 0xaa cci register index msb 0x169 0x5a 62 0x001 0x00 address 00xx ?? ?? 304 pre_pll_clk_div hi 63 0x295 0xa5 cci register index lsb 0x169 0x5a 64 0x101 0x40 address xx40 ?? ?? 305 pre_pll_clk_div lo 65 0x169 0x5a auto increment 0x169 0x5a 66 0x005 0x01 40 frame_format_model_type ?? ?? 306 pll_multiplier_hi 67 0x169 0x5a 0x169 0x5a 68 0x049 0x12 41 frame_format_model_subtyp e ?? ?? 307 pll_multiplier_lo 69 0x169 0x5a 0x169 0x5a 70 ?? ?? 42 frame_format_descriptor_0 hi ?? ?? 308 op_pix_clk_div hi 71 0x169 0x5a 0x169 0x5a 72 ?? ?? 43 frame_format_descriptor_0 lo ?? ?? 309 op_pix_clk_div lo 73 0x169 0x5a 0x169 0x5a 74 ?? ?? 44 frame_format_descriptor_1 hi ?? ?? 030a op_sys_clk_div hi 75 0x169 0x5a 0x169 0x5a 76 ?? ?? 45 frame_format_descriptor_1 lo ?? ?? 030b op_sys_clk_div lo 77 0x169 0x5a 0x2a9 0xaa cci register index msb 78 ?? ?? 46 frame_format_descriptor_2 hi 0x00d 0x03 address 03xx 79 0x169 0x5a 0x295 0xa5 cci register index lsb 80 ?? ?? 47 frame_format_descriptor_2 lo 0x101 0x40 address xx40 81 0x169 0x5a 0x169 0x5a auto increment 82 0x001 0x00 48 frame_format_descriptor_3 hi ?? ?? 340 frame_length_lines hi 83 0x169 0x5a 0x169 0x5a 84 0x001 0x00 49 frame_format_descriptor_3 lo ?? ?? 341 frame_length_lines lo 85 0x169 0x5a 0x169 0x5a 86 0x001 0x00 004a frame_format_descriptor_4 hi ?? ?? 342 line_length_pck hi 87 0x169 0x5a 0x169 0x5a 88 0x001 0x00 004b frame_format_descriptor_4 lo ?? ?? 343 line_length_pck lo table 6: embedded data row 0 row 1 offset 10-bit 8-bit two-wire serial interface address comment 10-bit 8-bit two- wire serial interface address comment
mt9d015: 1/5-inch 2 mp cmos digital image sensor embedded data format and control mt9d015_ds rev. m pub. 4/15 en 22 ?semiconductor components industries, llc,2015. 89 0x169 0x5a 0x169 0x5a 90 0x001 0x00 004c frame_format_descriptor_5 hi ?? ?? 344 x_addr_start hi 91 0x169 0x5a 0x169 0x5a 92 0x001 0x00 004d frame_format_descriptor_5 lo ?? ?? 345 x_addr_start lo 93 0x169 0x5a 0x169 0x5a 94 0x001 0x00 004e frame_format_descriptor_6 hi ?? ?? 346 y_addr_start hi 95 0x169 0x5a 0x169 0x5a 96 0x001 0x00 004f frame_format_descriptor_6 lo ?? ?? 347 y_addr_start lo 97 0x169 0x5a 0x169 0x5a 98 0x001 0x00 50 frame_format_descriptor_7 hi ?? ?? 348 x_addr_end hi 99 0x169 0x5a 0x169 0x5a 100 0x001 0x00 51 frame_format_descriptor_7 lo ?? ?? 349 x_addr_end lo 101 0x169 0x5a 0x169 0x5a 102 0x001 0x00 52 frame_format_descriptor_8 hi ?? ?? 034a y_addr_end hi 103 0x169 0x5a 0x169 0x5a 104 0x001 0x00 53 frame_format_descriptor_8 lo ?? ?? 034b y_addr_end lo 105 0x169 0x5a 0x169 0x5a 106 0x001 0x00 54 frame_format_descriptor_9 hi ?? ?? 034c x_output_size hi 107 0x169 0x5a 0x169 0x5a 108 0x001 0x00 55 frame_format_descriptor_9 lo ?? ?? 034d x_output_size lo 109 0x169 0x5a 0x169 0x5a 110 0x001 0x00 56 frame_format_descriptor_10 hi ?? ?? 034e y_output_size hi 111 0x169 0x5a 0x169 0x5a 112 0x001 0x00 57 frame_format_descriptor_10 lo ?? ?? 034f y_output_size lo 113 0x169 0x5a 0x2a9 0xaa cci register index msb 114 0x001 0x00 58 frame_format_descriptor_11 hi 0x00d 0x03 address 02xx 115 0x169 0x5a 0x295 0xa5 cci register index lsb 116 0x001 0x00 59 frame_format_descriptor_11 lo 0x201 0x80 address xx80 table 6: embedded data row 0 row 1 offset 10-bit 8-bit two-wire serial interface address comment 10-bit 8-bit two- wire serial interface address comment
mt9d015: 1/5-inch 2 mp cmos digital image sensor embedded data format and control mt9d015_ds rev. m pub. 4/15 en 23 ?semiconductor components industries, llc,2015. 117 0x169 0x5a 0x169 0x5a auto increment 118 0x001 0x00 005a frame_format_descriptor_12 hi ?? ?? 380 x_even_inc hi 119 0x169 0x5a 0x169 0x5a 120 0x001 0x00 005b frame_format_descriptor_12 lo ?? ?? 381 x_even_inc lo 121 0x169 0x5a 0x169 0x5a 122 0x001 0x00 005c frame_format_descriptor_13 hi ?? ?? 382 y_odd_inc hi 123 0x169 0x5a 0x169 0x5a 124 0x001 0x00 005d frame_format_descriptor_13 lo ?? ?? 383 y_odd_inc lo 125 0x169 0x5a 0x169 0x5a 126 0x001 0x00 005e frame_format_descriptor_14 hi ?? ?? 384 y_even_inc hi 127 0x169 0x5a 0x169 0x5a 128 0x001 0x00 005f frame_format_descriptor_14 lo ?? ?? 385 y_even_inc lo 129 0x2a9 0xaa cci register index msb 0x169 0x5a 130 0x001 0x00 address 00xx ?? ?? 386 x_odd_inc hi 131 0x295 0xa5 cci register index lsb 0x169 0x5a 132 0x201 0x80 address xx80 ?? ?? 387 x_odd_inc lo 133 0x169 0x5a auto increment 0x 2a9 0xaa cci register index msb 134 0x001 0x00 80 analogue_gain_capa bility hi 0x011 0x04 address 04xx 135 0x169 0x5a 0x295 0xa5 cci register index lsb 136 0x005 0x01 81 analogue_gain_capab ility lo 0x001 0x 00 address xx00 137 0x2a9 0xaa cci register index msb 0x169 0x5a auto increment 138 0x001 0x00 address 00xx ?? ?? 400 scaling_mode hi 139 0x295 0xa5 cci register index lsb 0x169 0x5a 140 0x211 0x84 address xx84 ?? ?? 401 scaling_mode lo 141 0x169 0x5a auto increment 0x169 0x5a 142 0x001 0x00 84 analogue_gain_code_min hi ?? ?? 402 spatial_sampling hi 143 0x169 0x5a 0x169 0x5a 144 0x021 0x08 85 analogue_gain_code_min lo ?? ?? 403 spatial_sampling lo 145 0x169 0x5a 0x169 0x5a 146 0x001 0x00 86 analogue_gain_code_max hi ?? ?? 404 scale_m hi 147 0x169 0x5a 0x169 0x5a 148 0x1fd 0x7f 87 analogue_gain_code_max lo ?? ?? 405 scale_m lo 149 0x169 0x5a 0x169 0x5a 150 0x001 0x00 88 analogue_gain_code_step hi 0x001 0x00 406 scale_n hi table 6: embedded data row 0 row 1 offset 10-bit 8-bit two-wire serial interface address comment 10-bit 8-bit two- wire serial interface address comment
mt9d015: 1/5-inch 2 mp cmos digital image sensor embedded data format and control mt9d015_ds rev. m pub. 4/15 en 24 ?semiconductor components industries, llc,2015. 151 0x169 0x5a 0x169 0x5a 152 0x005 0x01 89 analogue_gain_code_s tep lo 0x041 0x10 407 scale_n lo 153 0x169 0x5a 0x2a9 0xaa cci register index msb 154 0x001 0x00 008a analogue_gain_type hi 0x015 0x05 address 05xx 155 0x169 0x5a 0x295 0xa5 cci register index lsb 156 0x001 0x00 008b analogue_gain_type lo 0x001 0x00 address xx00 157 0x169 0x5a 0x169 0x5a auto increment 158 0x001 0x00 008c analogue_gain_m0 lo 0x001 0x00 500 compression_mode hi 159 0x169 0x5a 0x169 0x5a 160 0x005 0x01 008d analogue_gain_m0 lo 0x005 0x01 501 compression_mode lo 161 0x169 0x5a 0x2a9 0xaa cci register index msb 162 0x001 0x00 008e analogue_gain_c0 lo 0x019 0x06 address 06xx 163 0x169 0x5a 0x295 0xa5 cci register index lsb 164 0x001 0x00 008f analogue_gain_c0 lo 0x001 0x00 address xx00 165 0x169 0x5a 0x169 0x5a auto increment 166 0x001 0x00 90 analogue_gain_m1 lo ?? ?? 600 test_pattern_mode hi 167 0x169 0x5a 0x169 0x5a 168 0x001 0x00 91 analogue_gain_m1 lo ?? ?? 601 test_pattern_mode lo 169 0x169 0x5a 0x169 0x5a 170 0x001 0x00 92 analogue_gain_c1 lo ?? ?? 602 test_data_red hi 171 0x169 0x5a 0x169 0x5a 172 0x021 0x08 93 analogue_gain_c1 lo ?? ?? 603 test_data_red lo 173 0x2a9 0xaa cci register index msb 0x169 0x5a 174 0x001 0x00 address 00xx ?? ?? 604 test_data_greenr hi 175 0x295 0xa5 cci register index lsb 0x169 0x5a 176 0x301 0xc0 address xxc0 ?? ?? 605 test_data_greenr lo 177 0x169 0x5a auto increment 0x169 0x5a 178 0x005 0x01 00c0 data_format_model_type ?? ?? 606 test_data_blue hi 179 0x169 0x5a 0x169 0x5a 180 0x00d 0x03 00c1 data_format_model_subtype ?? ?? 607 test_data_blue lo 181 0x169 0x5a 0x169 0x5a 182 0x029 0x0a 00c2 data_format_descript or_0 hi ?? ?? 608 test_data_greenb hi 183 0x169 0x5a 0x169 0x5a 184 0x029 0x0a 00c3 data_format_descript or_0 lo ?? ?? 609 test_data_greenb lo 185 0x169 0x5a 0x169 0x5a 186 0x021 0x08 00c4 data_format_descriptor_1 hi ?? ?? 060a horizontal_cursor_width hi 187 0x169 0x5a 0x169 0x5a 188 0x021 0x08 00c5 data_format_descriptor_1 lo ?? ?? 060b horizo ntal_cursor_width lo 189 0x169 0x5a 0x169 0x5a table 6: embedded data row 0 row 1 offset 10-bit 8-bit two-wire serial interface address comment 10-bit 8-bit two- wire serial interface address comment
mt9d015: 1/5-inch 2 mp cmos digital image sensor embedded data format and control mt9d015_ds rev. m pub. 4/15 en 25 ?semiconductor components industries, llc,2015. 190 0x029 0x0a 00c6 data_format_descriptor_2 hi ?? ?? 060c horizont al_cursor_position hi 191 0x169 0x5a 0x169 0x5a 192 0x021 0x08 00c7 data_format_descriptor_2 lo ?? ?? 060d horizont al_cursor_position lo 193 0x169 0x5a 0x169 0x5a 194 0x001 0x00 00c8 data_format_descriptor_3 hi ?? ?? 060e vertical_cursor_width hi 195 0x169 0x5a 0x169 0x5a 196 0x001 0x00 00c9 data_format_descriptor _3 lo ?? ?? 060f vertical_cursor_width lo 197 0x169 0x5a 0x169 0x5a 198 0x001 0x00 00ca data_format_descriptor _4 hi ?? ?? 610 vertica l_cursor_position hi 199 0x169 0x5a 0x169 0x5a 200 0x001 0x00 00cb data_format_descriptor _4 lo ?? ?? 611 vertica l_cursor_position lo 201 0x169 0x5a 0x01d 0x07 null data 202 0x001 0x00 00cc data_format_descriptor_5 hi 0x01d 0x07 null data - up to end-of- line 203 0x169 0x5a 204 0x001 0x00 00cd data_format_descriptor_5 lo 205 0x169 0x5a 206 0x001 0x00 00ce data_format_descriptor_6 hi 207 0x169 0x5a 208 0x001 0x00 00cf data_format_descriptor_6 lo 209 0x2a9 0xaa cci register index msb 210 0x005 0x01 address 01xx 211 0x295 0xa5 cci register index lsb 212 0x001 0x00 address xx00 213 0x169 0x5a auto increment 214 ?? ?? 100 mode_select 215 0x169 0x5a 216 ?? ?? 101 image_orientation 217 0x169 0x5a 218 ?? ?? 102 reserved 219 0x169 0x5a 220 0x001 0x00 103 software_reset 221 0x169 0x5a 222 ?? ?? 104 grouped_parameter_hold 223 0x169 0x5a 224 ?? ?? 105 mask_corrupted_frames 225 0x2a9 0xaa cci register index msb table 6: embedded data row 0 row 1 offset 10-bit 8-bit two-wire serial interface address comment 10-bit 8-bit two- wire serial interface address comment
mt9d015: 1/5-inch 2 mp cmos digital image sensor embedded data format and control mt9d015_ds rev. m pub. 4/15 en 26 ?semiconductor components industries, llc,2015. 226 0x005 0x01 address 01xx 227 0x295 0xa5 cci register index lsb 228 0x041 0x10 address xx10 229 0x169 0x5a auto increment 230 ?? ?? 110 ccp2_channel_identifier 231 0x169 0x5a 232 ?? ?? 111 ccp2_signalling_mode 233 0x169 0x5a 234 ?? ?? 112 ccp_data_format_hi 235 0x169 0x5a 236 ?? ?? 113 ccp_data_format_lo 237 0x2a9 0xaa cci register index msb 238 0x005 0x01 address 01xx 239 0x295 0xa5 cci register index lsb 240 0x081 0x20 address xx20 241 0x169 0x5a auto increment 242 0x001 0x00 120 gain_mode 243 0x169 0x5a 244 ?? ?? 121 reserved 245 0x01d 0x07 null data 246 0x01d 0x07 null data - up to end-of-line table 6: embedded data row 0 row 1 offset 10-bit 8-bit two-wire serial interface address comment 10-bit 8-bit two- wire serial interface address comment
mt9d015_ds rev. m pub. 4/15 en 27 ?semiconductor components industries, llc,2015. mt9d015: 1/5-inch 2 mp cmos digital image sensor programming restrictions programming restrictions the smia specification imposes a number of programming restrictions. an implemen- tation naturally imposes additional restrictions. table 7 shows a list of programming rules that must be adhered to for correc t operation of the mt9d015. on semiconductor recommends that these rules are encoded into the device driver stack?either implicitly or explicitly. table 7: definitions for programming rules name definition xskip xskip = 1 if x_odd_inc = 1; xskip = 2 if x_odd_inc = 3 yskip yskip = 1 if y_odd_inc = 1; yskip = 2 if y_odd_inc = 3 table 8: programming rules parameter minimum value maximum value origin coarse_integration_time coarse_integration_time_min frame_length_lines - coarse_integration_time_max_margin smia fine_integration_time fine_integration_time_min line_length_pck - fine_integration_time_max_margin smia digital_gain_* digital_gain_min digital_gain_max smia digital_gain_* is an integer multiple of digital_gain_step_size smia frame_length_lines min_frame_length_lines max_frame_length_lines smia line_length_pck min_line_length_pck max_line_length_pck smia ((x_addr_end - x_addr_start + x_odd_inc)/xskip) + min_line_blanking_pck frame_length_lines ((y_addr_end - y_addr_start + y_odd_inc)/yskip) + min_frame_blanking_lines smia x_addr_start x_addr_min x_addr_max smia x_addr_end x_addr_start x_addr_max smia (x_addr_end - x_addr_start+ x_odd_inc) must be positive must be positive smia x_addr_start[0] 0 0 smia x_addr_end[0] 1 1 smia y_addr_start y_addr_min y_addr_max smia y_addr_end y_addr_start y_addr_max smia (y_addr_end - y_addr_start + y_odd_inc)/ must be positive must be positive smia y_addr_start[0] 0 0 smia y_addr_end[0] 1 1 smia x_even_inc min_even_inc max_even_inc smia x_even_inc[0] 1 1 smia y_even_inc min_even_inc max_even_inc smia y_even_inc[0] 1 1 smia x_odd_inc min _odd_inc max_odd_inc smia
mt9d015: 1/5-inch 2 mp cmos digital image sensor programming restrictions mt9d015_ds rev. m pub. 4/15 en 28 ?semiconductor components industries, llc,2015. notes: 1. with subsampling, start and end pixels must be addressed (impact on x/y start/end addresses, function of image orientatio n bits). smia fs errata see subsampling on page 44. output size restrictions the smia ccp2 specification imposes the rest riction that an outp ut line shall be a multiple of 32 bits in length. this imposes an additional restriction on the legal values of x_output_size: ? when ccp_format[7:0] = 8 (raw8 data), x_output_size must be a multiple of 4 (x_out- put_size[1:0] = 0). ? when ccp_format[7:0] = 10 (raw10 data), x_output_size must be a multiple of 16 (x_output_size[3:0] = 0). this restriction can be met by rounding up x_output_size to an appropriate multiple. any extra pixels in the output image as a resu lt of this rounding contain undefined pixel data but are guaranteed not to cause false synchronization on the ccp2 data stream. there is an additional restriction that x_outp ut_size must be small enough such that the output row time (set by x_output_size, the framing and crc overhead of 12 bytes, the ccp_signalling_mode and the ou tput clock rate) must be less than the row time of the video array (set by line_length_pc k and the video timing clock rate). x_odd_inc[0] 1 1 smia y_odd_inc min _odd_inc max_odd_inc smia y_odd_inc[0] 1 1 smia scale_m scaler_m_mi n scaler_m_max smia scale_n scaler_n_min scaler_n_max smia x_output_size 256 1608 minimum from smia fs section 5.2.2.5. maximum is a consequence of the output fifo size on this implementation. x_output_size[0] 0 (this is enforced in hardware: bit[0] is read-only) 0 smia fs section 5.2.2.2. y_output_size 2 frame_length_lines minimum ensures 1 bayer row-pair. maximum avoids output frame being longer than pixel array frame. y_output_size[0] 0 (this is enforced in hardware: bit[0] is read-only) 0 smia fs section 5.2.2.2 table 8: programming rules (continued) parameter minimum value maximum value origin
mt9d015_ds rev. m pub. 4/15 en 29 ?semiconductor components industries, llc,2015. mt9d015: 1/5-inch 2 mp cmos digital image sensor programming restrictions effect of scaler on legal range of output sizes when the scaler is enabled, it is necessary to adjust the values of x_output_size and y_output_size to match the image size gene rated by the scaler. the mt9d015 will not operate properly if the x_output_size and y_ou tput_size are significantly larger than the output image. to understand the reason for this, consider the situation where the sensor is operating at full resolution and the scaler is enabled with a scaling factor of 32 (half the number of pixels in each direction). this situation is shown in figure 11. figure 11: effect of limiter on the smia data path in figure 11, three different stages in the sm ia data path (see ?digital data path? on page 61) are shown. the first stage is the output of the sensor core. the core is running at full resolution and x_output_size is set to match the active array size. the line_valid (lv) signal is asserted once per row and remains asserted for n pixel times. the pixel_valid signal toggles with the same timing as lv, indicating that all pixels in the row are valid. the second stage is the output of the scaler, when the scaler is set to reduce the image size by one-half in each dimension. the effe ct of the scaler is to combine groups of pixels. therefore, the row time remains the same, but only half the pixels out of the scaler are valid. this is signalled by transitions in pixel_valid. overall, pixel_valid is asserted for ( n /2) pixel times per row. the third stage is the output of the limiter when the x_output_size is still set to match the active array size. because the scaler has reduced the amount of valid pixel data without reducing the row time, the limiter attempts to pad the row with ( n /2) additional pixels. if this has the effect of extending lv across th e whole of the horizontal blanking time, the mt9d015 will cease to generate output frames. a correct configuration is shown in figure 12 on page 30, in addition to showing the x_output_size reduced to match the output size of the scaler. in this configuration, the output of the limiter does not extend lv. figure 12 on page 30 also shows the effect of the output fifo, which forms the final stage in the smia data path. the output fifo merges the intermittent pixel data back into a contiguous stream. although not shown in this example, the output fifo is also capable of operating with an output clock that is at a different frequency from its input clock. core output: full resolution, x_output_size = x_addr_end - x_addr_start + 1 line_valid scaler output: scaled to half size line_valid pixel_valid limiter output: scaled to half size, x_output_size = x_addr_end - x_addr_start + 1 line_valid pixel_valid pixel_valid
mt9d015: 1/5-inch 2 mp cmos digital image sensor programming restrictions mt9d015_ds rev. m pub. 4/15 en 30 ?semiconductor components industries, llc,2015. figure 12: timing of smia data path effect of ccp2 class on legal range of output sizes/frame rate the pixel array readout rate is set by line_length_pck x frame_length_lines . with the default register values, one frame time takes 2360 x 1283 = 3027880 pixel periods. this value includes vertical and horizontal bl anking times so that the full-size image 1600 x 1202 (1200 lines of pixel data, 2 lines of em bedded information) forms a subset of these pixels. when the internal clock is running at 64 mhz, this frame time corresponds to 3027880/64e6 = 47.31 ms, giving rise to a frame rate of 21.14 fps. each pixel is 10 bits, by default. as a result, the serial data rate is required to transmit faster than the pixel rate. however, the smia ccp2 class 2 specifications has a maximum of 650 mb/s, which cannot be exceeded. the smia ccp2 specification shows that cl ass 0 (data/clock) runs up to 208 mb/s. therefore, it is not possible to transmit full-resolution images at 15 fps using ccp2 class 0. changing the ccp_data_format (to use 8 bits per pixel) reduces the bandwidth require- ment, but is not enough to al low full-resolution operation. the only way to get a full image out is to redu ce the pixel clock rate until it is appropriate for the maximum ccp2 class 0 data rate. this requires the pixel rate to be reduced to 20.8 mhz. this has the side effect of reducing the frame rate. repeating the calculation above, at 20.8 mhz internal clock, this corresponds to 3027880/20.8e6 = 14 5 ms, giving rise to a frame rate of 6.87 fps. to use ccp2 class 0 with an internal clock of 64 mhz, it is necessary to reduce the amount of output data. this can be achieved by changing x_output_size, y_output_size so that less data comes out per frame. a change to the output size can be done in conjunction with windowing the image from the sensor (by adjusting x_addr_start, x_addr_end, y_addr_start, y_addr_end ) or by enabling the scaler. core output: full resolution, x_output_size = x_addr_end - x_addr_start + 1 line_valid scaler output: scaled to half size line_valid pixel_valid limiter output: scaled to half size, x_output_size = (x_addr_end - x_addr_start + 1)/2 pixel_valid line_valid pixel_valid output fifo: scaled to half size, x_output_size = (x_addr_end - x_addr_start + 1)/2 line_valid pixel_valid
mt9d015: 1/5-inch 2 mp cmos digital image sensor programming restrictions mt9d015_ds rev. m pub. 4/15 en 31 ?semiconductor components industries, llc,2015. output data timing the output fifo acts as a boundary between two clock domains. data is written to the fifo in the vt (video timing) clock domain. data is read out of the fifo in the op (output) clock domain. when the scaler is disabled, the data rate in the vt clock domain is constant and uniform during the active period of each pi xel array row readout. when the scaler is enabled, the data rate in the vt clock domain becomes intermittent, corresponding to the data reduction performed by the scaler. maximum frame rate is achieved by setting the video timing clock (vt_clk_freq_mhz) to 91 mhz and using the fifo to reduce horizontal blanking data rate to 640 mb/s. at this setting, a maximum frame rate of 30 fps can be achieved. a key constraint when configuring the clock fo r the output fifo is that the frame rate out of the fifo must exactly match the frame rate into the fifo. when the scaler is disabled, this constraint can be met by imposi ng the rule that the row time on the ccp2 data stream must be greater than or equal to the row time at the pixel array. the row time on the ccp2 data stream is calculated fr om the x_output_size and the ccp_data_format (8 or 10 bits per pixel), and must include the time taken in the ccp2 data stream for start of frame/row, end of row/ frame and checksum symbols. caution if this constraint is not met, the fifo will either underrun or overrun. fifo underrun or over- run is a fatal error condition that is signalled through the data path_status register (r0x306a). changing registers while streaming the following registers should only be repr ogrammed while the sensor is in software standby: ? ccp2_channel_identifier ? ccp2_signalling_mode ? ccp_data_format ?scale_m ?vt_pix_clk_div ? vt_sys_clk_div ? pre_pll_clk_div ? pll_multiplier ? op_pix_clk_div ?op_sys_clk_div
mt9d015: 1/5-inch 2 mp cmos digital image sensor control of the signal interface mt9d015_ds rev. m pub. 4/15 en 32 ?semiconductor components industries, llc,2015. control of the signal interface this section describes the operation of the signal interface in all functional modes. serial register interface the serial register interface uses the following signals: ?s clk ?s data s clk is an input-only signal and must always be driven to a valid logic level for correct operation; if the driving device can place this signal in high-z state, an external pull-up resistor should be connected on this signal. s data is a bidirectional signal. an external pull-up resistor should be connected on this signal. this interface is described in detail in ?extclk? on page 66. default power-up state the mt9d015 provides interfaces for pixel data through the ccp2 high-speed serial interface described by the smia specification or the mipi serial interface. at power up and after a hard or soft reset, the reset state of the mt9d015 is to enable the smia ccp2 high speed serial interface fo r a ccp2-configured sensor, and csi-2 high speed serial interface for a mipi-configured sensor. the ccp2 and mipi serial interfaces share pins, and only one can be enabled at time. this is done at the factory.
mt9d015: 1/5-inch 2 mp cmos digital image sensor control of the signal interface mt9d015_ds rev. m pub. 4/15 en 33 ?semiconductor components industries, llc,2015. serial pixel data interface the serial pixel data interface uses the following output-only signal pairs: ?data_p ?data_n ?clk_p ?clk_n the signal pairs are driven differentially using sub-lvds switching levels. this interface conforms to the mipi 1.0 csi-2 and smia ccp2 requirements and supports both data/ clock signalling and da ta/strobe signalling. the serial pixel data interface is enabled by default at power up and after reset. data_p and data_n are the data pair for the ccp2 or mipi serial interface. the data_p, data_n, clk_p, and clk_n pads are turned off if the smia serial disable bit is asserted (r0x301a?b[12] = 1) or when the sensor is in the soft standby state. in data/clock mode, the clock remains high wh en no data is being transmitted. in data/ strobe mode before frame start, clock is low and data is high. r0x0112-3 (ccp_data_format) the foll owing data formats are supported: ? 0x0a0a ? sensor supports raw10 uncompressed data format. ? 0x0808 ? sensor supports raw8 uncompressed data format. a sensor with a 10-bit adc can support this mode by discarding all but the upper 8 bits of a pixel value. ? 0x0a08 ? sensor supports raw8 data format in which an adaptive compression algo- rithm is used to perform 10-bit to 8-bit comp ression on the upper 10 bits of each pixel value. also, the ccp_serial_format register (r0x31ae) register controls which serial interface is in use when the serial interface is enabled (reset_register[12] = 0). the following serial formats supported: ? 0x0101 ? sensor supports single-lane ccp2 operation. ? 0x0201 ? sensor supports single-lane mipi operation.
mt9d015: 1/5-inch 2 mp cmos digital image sensor control of the signal interface mt9d015_ds rev. m pub. 4/15 en 34 ?semiconductor components industries, llc,2015. system states the system states of the mt9d015 are repr esented as a state diagram in figure 13 and described in subsequent sections. the effect of reset_bar on the system state and the configuration of the pll in the different states are shown in table 9 on page 35. the sensor?s operation is broken down into th ree separate states: hardware standby, soft standby, and streaming. the transition be tween these states might take a certain amount of clock cycles as outlined in table 9. figure 13: mt9d015 system states powered off por active internal init (1200 extclks) software standby streaming wait for frame/row end pll lock (16000 extclks) software reset powered on por completed hardware reset released init finished por not yet completed init not completed pll aquiring lock mode_select =1 lock acquired mode_select = 0 frame in progress 1> hardware standby hardware reset active reset transition - 0 (asynchronous from every state ) power supply turned off (asynchronous from every state )
mt9d015: 1/5-inch 2 mp cmos digital image sensor control of the signal interface mt9d015_ds rev. m pub. 4/15 en 35 ?semiconductor components industries, llc,2015. note: vco = voltage-controlled oscillator. power-on reset sequence when power is applied to the mt9d015, it enters a low-power hardware standby state. exit from this state is controlled by the later of two events: 1. the negation of the reset_bar input. 2. a timeout of the internal power-on reset circuit. it is possible to hold reset_bar permanently negated and rely upon the internal power-on reset circuit. when reset_bar is asserted, it asynchronous ly resets the sensor, truncating any frame that is in progress. when the sensor leaves the hardware standb y state, it waits for power-on reset and performs an internal initialization sequence that takes 1200 extclk cycles. after this time, it enters a low-power soft standby state. while the initialization sequence is in progress, the mt9d015 will not respond to re ad transactions on its two-wire serial interface. therefore, a method to determine when the initialization sequence has completed is to poll a sensor register; for example, r0x0000. while the initialization sequence is in progress, the sensor will not respond to its device address and reads from the sensor will result in a nack on the two-wire serial interface bus. when the sequence has completed, reads will return the operational value for the register (0x1501 if r0x0000 is read). when the sensor leaves soft standby mode and enables the vco, an internal delay will keep the pll disconnected for up to 16000 extclks so that the pll can lock. soft reset sequence the mt9d015 can be reset under software control by writing ?1? to software_reset (r0x0103). a software reset asynchronously re sets the sensor, truncating any frame that is in progress. the sensor starts the intern al initialization sequence, while the pll and analog blocks are turned off. at this point, the behavior is exactly the same as for the power-on reset sequence. table 9: pll in system states state extclks pll powered off hardware standby por active internal initialization 1200 vco powered down software standby pll lock 16000 vco powering up and locking, pll output bypassed streaming vco running, pll output active wait for frame end
mt9d015: 1/5-inch 2 mp cmos digital image sensor control of the signal interface mt9d015_ds rev. m pub. 4/15 en 36 ?semiconductor components industries, llc,2015. signal state during reset table 10 shows the state of the signal inte rface during hardware standby (reset_bar asserted) and the default state during soft st andby (after exit from hardware standby and before any registers within the sensor have been changed from their default power-up values). general purpose inputs the mt9d015 provides four general purpose inputs. after reset, the input pads associ- ated with these signals are powered on by de fault, requiring the pads to be tied to a defined logic level. the general purpose inputs are disabled by setting reset_register[8] (r0x301a?b). once disabled, the inputs can be left floating. the state of the general purpose inputs can be read through gpi_status[3:0] (r0x3026?7). streaming/standby control the mt9d015 can be switched between its soft standby and streaming states under register control, as shown in table 11. th e state diagram for transitions between soft standby and streaming states is shown in figure 13 on page 34. table 10: signal state during reset pad name pad type hardware standby software standby extclk input self-biased. can be left disconnected/floating. reset_bar (xshutdown) input enabled. must be driven to a valid logic level. s clk input enabled. must be pulled up or driven to a valid logic level. s data i/o enabled as an input. must be pulled up or driven to a valid logic level. data_p output ccp2: high-z mipi: ultra low-power state (ulps), represented as an lp-00 state on the output (both wires at 0v) data_n output clk_p output clk_n output gpi[3:0] input powered up. must be connected to v dd or d gnd . test input enabled. must be driven to a logic 0 for a serial ccp2-configured sensor, or 1 for a serial mipi-configured sensor. table 11: streaming/standby streaming r0x301aCb[2] or r0x0100[0] description 0 soft standby 1streaming
mt9d015: 1/5-inch 2 mp cmos digital image sensor clocking mt9d015_ds rev. m pub. 4/15 en 37 ?semiconductor components industries, llc,2015. clocking the mt9d015 contains a pll for timing gene ration and control. the pll contains a prescaler to divide the input clock applied on extclk, a vco to multiply the prescaler output, and a set of dividers to generate the output clocks. profile 0 behavior on semiconductor smia sensors are profile 2 sensors and have separate video timing and output clock domains. if the video timing and output clock domains are programmed with the same dividers, the part will operate in profile 0 mode as indicated by r0x306e?f[7]. for example, if equation 1 is true, then the pll will have profile 0 behavior: profile0_behavior = (vt_sys_clk_div == op_sys_clk_div) (eq 1) & (vt_pix_clk_div == op_pix_clk_div) when the pll is programmed to be in profile 0 behavior then the output clock domain is connected internally to the video timing doma in thus ensuring that the sensor behave as an profile 0 sensor with respect to the pll. in profile 0 mode the number of bits between one sync code and the subsequent one are guaranteed to be equal. note that legacy sensors used the profile bit in the datapath_select register r0x306e[7] to set this behavior. the new behavior of profile 0 mode is equivalent with the old one once it is set by the host system.
mt9d015: 1/5-inch 2 mp cmos digital image sensor clocking mt9d015_ds rev. m pub. 4/15 en 38 ?semiconductor components industries, llc,2015. figure 14: mt9d015 smia profile 1/2 clocking structure notes: 1. the combinations vt_sys_clk_d iv = 1 and vt_pix_clk_div = (4,5, 6,... 16) are also supported even though the capability register does not advertise this. 2. the pll_multiplier only accepts even values when ccp 2_class is set to data/clock signalling. odd val- ues will be rounded down to the first even number by setting lsb to 0. 3. the default value for vt_sys_clk_div is outside th e range of legal values defined by the capability registers. this results in correct behavior for th e cases listed in note 1. the default setting is selected to ensure profile 0 behavior as de fault with the highest possible frame rate. the parameter limit register space contains registers that declare the minimum and maximum allowable values for: ? the frequency allowable on each clock ? the divisors that are used to control each clock the following factors determine what are vali d values, or combinations of valid values, for the divider/multiplier control registers: ? the minimum/maximum frequency limits for the associated clock must be met. ? the minimum/maximum value for the divider/multiplier must be met. ? the value of pll_multiplier should be a multiple of 2 for data/strobe signalling. ? the op_pix_clk must never run faster than the vt_pix_clk to ensure that the ccp2 output data stream is contiguous. ? given the maximum programmed line length, the minimum blanking time, the maximum image width, the available pll di visor/multiplier values, and the require- ment that the output line ti me (including the necessary bl anking) must be output in a time equal to or less than the time defined by line_length_pck, the valid combinations of the clock divisors. pll input clock frequency range, after the pre-pll divider stage, is 2.0?24 mhz. the usage of the output clocks is: ? vt_pix_clk is used by the sensor core to control the timing of the pixel array. the sensor core produces one 10-bit pixel each vt_pix_clk period. the line length pre pll divider vt _sys_clk divider pll multiplier vt _ pix _clk divider op_sys _clk divider op _pix _clk divider op_pix_clk extclk external input clock pll input clock pll output clock video timing system clock op _ pix _clk _ div 10( 8, 10) pll_op_clk_freq_mhz pll_ip_clk_freq_mhz vt_sys_clk_freq_mhz vt_sys_clk_div 1 (1, 2,4,6 ... 16) vt_pix_clk op_sys_clk_div 1(1,2,4,6...16) vt_sys_clk_freq_mhz op_sys_clk pll_multiplier 80(16,18 .....256) pre_pll_clk_div 2(1, 2, 3.....64) ext_clk_freq_mhz vt_pix_clk_div 10 (4, 5, 6...16) 1
mt9d015: 1/5-inch 2 mp cmos digital image sensor clocking mt9d015_ds rev. m pub. 4/15 en 39 ?semiconductor components industries, llc,2015. (line_length_pck) and fine integration time (fine_integration_time) are controlled in increments of the vt_pix_clk period. ? op_pix_clk is used to load parallel pixel data from the output fifo (see figure 26 on page 61) to the ccp2 serializer. the output fifo generates one pixel each op_pix_clk period. the pixel is either 8-bit or 10-bit depending upon the output data format, controlled by r0x0112 -3 (ccp_data_format). ? op_sys_clk is used to generate the serial data stream on the ccp2 output. the rela- tionship between this clock frequency an d the op_pix_clk frequency is dependent upon the output data format. in profile 1/2, the output clock frequencies can be calculated as: (eq 2) (eq 3) (eq 4) figure 15: mt9d015 smia profile 0 clocking structure notes: 1. the legal range yielding profile 0 behavior is lim ited to the pll values wh ere the vt domain equals the op domain. the vt_sys_clk_div values in the parentheses are therefore the legal values for both vt_sys_clk_div and op_sys_clk_div, and the vt _pix_clk_div values in the parentheses are legal values for both vt_pix_clk _div and op_pix_clk_div. 2. the default value for vt_sys_clk_div is outside th e range of legal values defined by the capability registers. this will result in co rrect behavior for the cases listed in note 1. the default setting is selected to ensure profile 0 behavior as de fault with the highest possible frame rate. when the video timing domain and the outp ut timing domain have the same divider values, the pll is equivalent to the smia profile 0 clocking structure. this is achieved by driving the op_sys_clk domain from the vt_sys_clk output and by driving the op_pix_clk domain from the vt_pix_clk output. vt_pix_clk_freq_mhz = ext_clk_freq_mhz*pll_multiplier pre_pll_clk_div*vt_sys _clk_div*vt_pix_clk_div ------------------ --------------------- ---------------------- --------------------- ------------------ ------------- op_pix_clk_freq_mhz = ext_clk_freq_mhz*pll_multiplier pre_pll_clk_div*op_sys _clk_div*op_pix_clk_div -------------------- --------------------- --------------------- --------------------- ------------------ --------------- - op_sys_clk_freq_mhz = ext_clk_freq_mhz*pll_multiplier pre_pll_clk_div*op_sys_clk_div -------------------- --------------------- --------------------- ----------------- pre pll divider vt_sys_ clk divider pll multiplier vt_pix_clk divider extclk external input clock pll input clock pll output clock video timing system clock vt_sys_clk_div 1 (1, 2,4,6...16) pll_op_clk_freq_mhz pll_ip_clk_freq_mhz vt_sys_clk_freq_mhz ext_clk_freq_mhz pll_multiplier 80 (16,18....256) pre_pll_clk_div 2 (1,2,3,4....64) vt_pix_clk vt_pix_clk_div 10 (4,5, 6...16) op_sys_clk
mt9d015: 1/5-inch 2 mp cmos digital image sensor clocking mt9d015_ds rev. m pub. 4/15 en 40 ?semiconductor components industries, llc,2015. programming the pll divisors the pll divisors should be programmed while the mt9d015 is in the soft standby state. after programming the divisors, it is necessary to wait for the vco lock time before enabling the pll. the pll is enabled by entering the streaming state. an external timer needs to delay the entering of streaming mode by 1ms so that the pll can lock. the effect of programming the pll divisors while the mt9d015 is in the streaming state is undefined. influence of ccp_data_format r0x0112-3 (ccp_data_form at) controls whether the pixel data interface will generate 10 bits per pixel or 8 bits per pixel. the raw output of the sensor core is 10 bits per pixel; the two 8-bit modes represent a compressed data mode and a mode in which the two least significant bits of the 10-bit data are discarded. when the pixel data interface is generating 8 bits per pixel, op_pix_clk_div must be programmed with the value 8. when the pixel data interface is generating 10 bits per- pixel, op_pix_clk_div must be programmed with the value 10.
mt9d015: 1/5-inch 2 mp cmos digital image sensor features mt9d015_ds rev. m pub. 4/15 en 41 ?semiconductor components industries, llc,2015. features lens shading correction (lc) lenses tend to produce images whose bright ness is significantly attenuated near the edges. there are also other factors causing fixed pattern signal gradients in images captured by image sensors. the cumulative result of all these factors is known as image shading. the mt9d015 has an embedded sh ading correction module that can be programmed to counter the shading effects on each individual red, greenb, greenr, and blue color signal. the correction function color-dependent solutions are calibrated using the sensor, lens system, and an image of an evenly illuminated, featureless grey cali bration field. from the resulting image the color correction functions can be derived. the correction functions can then be appl ied to each pixel value to equalize the response across the image as follows: (eq 5) where p are the pixel values and f is the color-dependent correction function for each color channel. each function includes a set of color-dependent coefficients defined by registers r0x3600?3726. the function's origin is the ce nter point of the function used in the calculation of the coefficients. using an origin near the central point of symmetry of the sensor response provides the best results. the correct sequence to write to the lc registers is as follows: 1. set r0x3780?1 = 0x0000. 2. load lc coefficients. 3. set r0x3780?1 = 0x8000. to read the lc coefficients, disable lc (set r0x3780?1 = 0x0000) before reading the register values. one-time programmable memory (otpm) the mt9d015 has 2624 bits of otp memory that can be used during module manufac- turing to store specific module information. this feature enables system integrators and module manufacturers to label and distingu ish various module types based on lenses, ir-cut filters, or other prop erties. mt9d015 can support one set of lsc to save in otpm. for otpm programming details, please refer tn-09-248. pcorrected row, col ?? = psensor(row,col) * f(row,col)
mt9d015: 1/5-inch 2 mp cmos digital image sensor features mt9d015_ds rev. m pub. 4/15 en 42 ?semiconductor components industries, llc,2015. figure 16: otpm block diagram image acquisition modes the mt9d015 supports ers mode. when the mt9d015 is streaming, it generates frames at a fixed rate, and each frame is integrated (exposed) using the ers. timing and control logic within the sensor sequences through th e rows of the array, resetting and then reading each row in turn. in the time interval between resetting a row and subsequently reading that row, the pixels in the row integrate incident light. the integration (expo- sure) time is controlled by varying the time between row reset and row readout. for each row in a frame, the time between row reset an d row readout is fixed, leading to a uniform integration time across the frame. when the integration time is changed (by using the two-wire serial interface to change regist er settings), the timing and control logic controls the transition from ol d to new integration time in such a way that the stream of output frames from the mt9d015 switches c leanly from the old integration time to the new while only generating frames with uniform integration. window control the sequencing of the pixel array is contro lled by the x_addr_start, y_addr_start, x_ad- dr_end, and y_addr_end registers. the output image size is controlled by the x_output_- size and y_output_size registers. pixel border the default settings of the sensor provide a 1600h x 1200v image. a border of up to 4 pixels on each edge can be enabled by re programming the x_addr_start, y_addr_start, x_addr_end, y_addr_end, and x_output_size and y_output_size registers accordingly. registers (cache) for transferring the data to otpm 4 kbits maximum (r0x3800 to r0x39fe) otpm control (r0x304a) record type range from 0x30 - 0x39, 0x50--0xff, and 0x15--0x1f (r0x304c) actual otpm memory in hardware - 2624 bits trigger to write or read otpm write or read data from otpm after trigger program the record type record type data 0x30 0x31 1 bit to 4 kbits 1 bit to 4 kbits 1 bit to 4 kbits 1 bit to 4 kbits 0xfe 0xff
mt9d015: 1/5-inch 2 mp cmos digital image sensor features mt9d015_ds rev. m pub. 4/15 en 43 ?semiconductor components industries, llc,2015. full resolution frame structure with embedded data figure 17 shows a full resolution frame structure example. the embedded data enable or disable is controlled by r0x30 64[8], when set the bit to "1", two lines of embedded data will output on start of image frame. figure 17: full resolution frame structure example readout modes horizontal mirror when the horizontal_mirror bit is set in the image_orientation register, the order of pixel readout within a row is reversed, so that re adout starts from x_addr_end and ends at x_addr_start. figure 18 shows a sequence of 6 pixels being read out with horizon- tal_mirror = 0 and horizontal_mirror = 1. changing horizontal_mirror causes the bayer order of the output image to change; the new bayer order is reflected in the value of the pixel_order register. figure 18: effect of horizontal_mirror on readout order 2 embedded data lanes fs ls le n manufacture specific rows visible pixels up to 1608 x 1208 fe checksums frame blanking line blanking g0 [9:0] r0 [9:0] g1 [9:0] r1 [9:0] g2 [9:0] r2 [9:0] r2 [9:0] g2 [9:0] r1 [9:0] g1 [9:0] r0 [9:0] g0 [9:0] line_valid horizontal_mirror = 0 d out (9:0) horizontal_mirror = 1 d out (9:0)
mt9d015: 1/5-inch 2 mp cmos digital image sensor features mt9d015_ds rev. m pub. 4/15 en 44 ?semiconductor components industries, llc,2015. vertical flip when the vertical_flip bit is set in the image_orientation register, the order in which pixel rows are read out is reversed, so that row readout starts from y_addr_end and ends at y_addr_start. figure 19 shows a sequence of 6 rows being read out with vertical_flip = 0 and vertical_flip = 1. changing vertical_flip causes the bayer order of the output image to change; the new bayer order is reflected in the value of the pixel_order register. figure 19: effect of vertical_flip on readout order subsampling the mt9d015 supports subsampling. subs ampling reduces the amount of data processed by the analog signal chain in the mt9d015 thereby allowing the frame rate to be increased. subsampling is enabled by se tting x_odd_inc and/or y_odd_inc. values of 1 and 3 can be supported. setting both of th ese variables to 3 reduces the amount of row and column data processed. figure 20 shows a sequence of 8 columns being read out with x_odd_inc = 3 and y_odd_inc = 1. figure 20: effect of x_odd_inc = 3 on readout sequence row0 [9:0] row1 [9:0] row2 [9:0] row3 [9:0] row4 [9:0] row5 [9:0] row5 [9:0] row4 [9:0] row3 [9:0] row2 [9:0] row1 [9:0] row0 [9:0] frame_valid vertical_flip = 0 d out( 9:0) vertical_flip = 1 d out (9:0) g0 [9:0] r0 [9:0] g1 [9:0] r1 [9:0] g2 [9:0] r2 [9:0] g3 [9:0] r3 [9:0] g0 [9:0] r0 [9:0] g2 [9:0] r2 [9:0] line_valid x_odd_inc = 1 d out [9:0] line_valid x_odd_inc = 3 d out [9:0]
mt9d015: 1/5-inch 2 mp cmos digital image sensor features mt9d015_ds rev. m pub. 4/15 en 45 ?semiconductor components industries, llc,2015. figure 21: pixel readout (no subsampling) figure 22: pixel readout (x_odd_inc = 3, y_odd_inc = 3) programming restrictio ns when subsampling when subsampling is enabled as a viewfinder mode and the sensor is switched back and forth between full resolution and subsampling, on semiconductor recommends that line_length_pck be kept consta nt between the two modes. this allows the same integra- tion times to be used in each mode. when subsampling is enabled, it may be necessary to adjust the x_addr_end, x_ad- dr_start and y_addr_end settings: the values for these registers are required to corre- spond with rows/columns that form part of the subsampling sequence. the adjustment should be made in accordance with the following rules: ? x_addr_start must be a multiple of 2 for example 0, 4, 6, 8, and x_addr_start = 2 is not supported example: to achieve 1600 x 1200 full resolution with out subsampling, the recommended register settings are: x incrementing y incrementing x incrementing y incrementing
mt9d015: 1/5-inch 2 mp cmos digital image sensor features mt9d015_ds rev. m pub. 4/15 en 46 ?semiconductor components industries, llc,2015. [full resolution starting address with (4, 4)] reg=0x0104, 1 //grouped_parameter_hold reg=0x0382, 1 //x_odd_inc reg=0x0386, 1 //y_odd_inc reg=0x0344, 4 //x_addr_start reg=0x0346, 4 //y_addr_start reg=0x0348, 1603 //x_addr_end reg=0x034a, 1203 //y_addr_end reg=0x034c, 1600 //x_output_size reg=0x034e, 1200 //y_output_size reg=0x0104, 0 //grouped_parameter_hold
mt9d015: 1/5-inch 2 mp cmos digital image sensor features mt9d015_ds rev. m pub. 4/15 en 47 ?semiconductor components industries, llc,2015. to achieve a 800 x 600 resolution with 1/2 subsampling, the recommended register settings are: table 12 shows the row address sequencing for normal and subsampled readout. the same sequencing applies to column addresses for subsampled readout. there are two possible subsampling sequences for the rows (because the subsampling sequence only read half of the rows) depending upon the alignment of the start address. [1/2 subsampling starting address with (8, 8)] reg=0x0104, 1 //grouped_parameter_hold reg=0x0382, 3 //x_odd_inc reg=0x0386, 3 //y_odd_inc reg=0x0344, 8 //x_addr_start reg=0x0346, 8 //y_addr_start reg=0x0348, 1605 //x_addr_end reg=0x034a, 1205 //y_addr_end reg=0x034c, 800 // x_output_size reg=0x034e, 600 //y_output_size reg=0x0104, 0 //grouped_parameter_hold table 12: row address sequencing odd_inc = 1 odd_inc = 3 normal normal start = 0 start = 0 start = 2 00 11 22 33 44 55 66 77 88 99 10 10 11 11 12 12 13 13 14 14 15 15
mt9d015: 1/5-inch 2 mp cmos digital image sensor features mt9d015_ds rev. m pub. 4/15 en 48 ?semiconductor components industries, llc,2015. frame rate control the formula for calculating the frame rate of the mt9d015 are shown below: (eq 6) (eq 7) (eq 8) note: subsampling factor = xskip or yskip xskip = 1 if x_odd_inc = 1; xskip = 2 if x_odd_inc = 3 yskip = 1 if y_odd_inc = 1; yskip = 2 if y_odd_inc = 3 minimum row time the minimum row time and blanking values with default register settings are shown in tabl e 13 . in addition, enough time must be given to the output fifo so it can output all data at the set frequency within one row time. there are therefore three checks that must all be met when programming line_length_pck: ? line_length_pck > min_line_length_pck in table 13. ? line_length_pck > (x_addr_end - x_addr_start + x_odd_inc)/((1+x_odd_inc)/2) + min_line_blanking_pck in table 13. ? the row time must allow the fifo to output all data during each row. that is, line_length_pck > (x_output_size / 2 ) * (vt_pix_clk_freq)/(op_pix_clk_freq) minimum frame time the minimum number of rows in the image is 2, so min_frame_length_lines will always equal (min_frame_blanking_lines + 2). table 13: minimum row time and blanking numbers row_speed[2:0] 1 2 4 min_line_blanking_pck 0x02e1 0x01c9 0x013d min_line_length_pck 0x03e1 0x0370 0x02e0 table 14: minimum frame time and blanking numbers min_frame_blanking_lines 0x0093 min_frame_length_lines 0x054b line_length_pck x_addr_end - x_addr_start x_odd_inc + subsampling factor -------------------- --------------------- --------------------- ------------------ ----------------- - min_line_blanking_pck + ?? ?? = frame_length_lines y_addr_end - y_addr_start y_odd_inc + subsampling factor --------------------- --------------------- ---------------------- ----------------- ---------------- - min_frame_blanking_lines + ?? ?? = frame rate [fps] vt_pixel_clock_mhz * 1 6 ? 10 ?? line_length_pck* frame_length_lines ?? --------------------- --------------------- ------------------ ----------------- ----------------- - =
mt9d015: 1/5-inch 2 mp cmos digital image sensor features mt9d015_ds rev. m pub. 4/15 en 49 ?semiconductor components industries, llc,2015. integration time the integration (exposure) time of the mt9d015 is controlled by the fine_integration_- time and coarse_integration_time registers. the limits for the fine inte gration time are defined by: (eq 9) the limits for the coarse integration time are defined by: (eq 10) if coarse_integration_time > (frame_lenth_l ines-coarse_integration_time_max_margin), then the frame rate will be reduced. the actual integratio n time is given by: (eq 11) with a vt_pix_clk of 64 mhz, the maximum integration time that can be achieved without reducing the frame rate is given by: (eq 12) setting an integration time that is greater than the frame time increases the frame time beyond frame_leng th_lines to make longer exposure times available. fine integration time limits the limits for the fine_integration_time ca n be found from fine _integration_ time_min and fine_integration_time_max_margin. values for different mode combinations are shown in table 15. table 15: fine_integration_time limits row_speed[2:0] 1 2 4 fine_integration_time_min 0x01e5 0x0104 0x0052 fine_integration_time_max_margin 0x0191 0x00b7 0x008b fine_integration_time_min < = fine_integration_time < = line_length_pck-fine_integration_time_max_margin ?? coarse_integration_time_min < = coarse_integration_t integration_time [sec] coarse_integration_time * line_length_pck ?? fine_integration_time + ?? vt_pix_clk_freq_mhz*1*10 6 ?? ------------------------------------------------------------------------------------------------------------------------------- ------------------------------------------- = maximum integration time [sec] = (( frame_length_lines -1 ?? * line_length_pck) + (line_length_pck - fine_integration_time_max_margin) vt_pix_clk_freq_mhz * 1* 10 6 ?? -------------------- --------------------- ----------------- ------------------ ------------------ ----------------- ---------------- -------------------- --------------------- --------------------- --------------------- ---------------------- ------------------ = 0x0503 ?? *0x0938 ?? +0x7a3 ?? 64 mhz*1*10 6 ?? --------------------------------------------------------------------------------------- 47.34 ms =
mt9d015: 1/5-inch 2 mp cmos digital image sensor features mt9d015_ds rev. m pub. 4/15 en 50 ?semiconductor components industries, llc,2015. analog gain the mt9d015 provides two mechanisms for setting the analog gain. the first uses the smia gain model; the second uses the tr aditional on semiconductor gain model. the following sections describe both models, the mapping between the models, and the operation of the per-color and global gain control. using per-color or global gain control the read-only analogue_gain_capa bility register returns a value of ?1,? indicating that the mt9d015 provides per-color gain control. however, the mt9d015 also provides the option of global gain control. per-color an d global gain control can be used interchange- ably. a write to a global gain register is alia sed as a write of the same data to the four associated color-dependent gain registers. a read from a global gain register is aliased to a read of the associated greenb/greenr gain register. the read/write gain mode register required by smia has no defined function in the smia specification. in the mt9d015 this register has no side effects on the operation of the gain; per-color and global gain control can be used interchangeably regardless of the state of the gain_mode register.
mt9d015: 1/5-inch 2 mp cmos digital image sensor features mt9d015_ds rev. m pub. 4/15 en 51 ?semiconductor components industries, llc,2015. smia gain model the smia gain model uses the following registers to set the analog gain: ? analogue_gain_code_global ? analogue_gain_code_greenr ? analogue_gain_code_red ? analogue_gain_code_blue ? analogue_gain_code_greenb the smia gain model requires a uniform step size between all gain settings. the analog gain is given by: (eq 13) on semiconductor gain model the on semiconductor gain model uses the following registers to set the analog gain: ? global_gain ?greenr_gain ? red_gain ? blue_gain ?greenb_gain this gain model maps directly to the control settings applied to the gain stages of the analog signal chain. this prov ides a 7-bit gain stage and a number of 2x gain stages. as a result, the step size varies depending upon whether the 2x gain stages are enabled. the analog gain is given by: (eq 14) as a result of the 2x gain stage, many of the possible gain settings can be achieved in two different ways. in all cases, the preferred setting is the setting that uses _gain[7] first, _gain[6:0] , and then _gain[8] to apply the desired gain range,, because this will result in lower noise. gain code mapping the on semiconductor gain model maps directly to the underlying structure of the gain stages in the analog signal chain. when the smia gain model is used, gain codes are translated into equivalent settings in the on semiconductor gain model. when the smia gain model is in use and values have been written to the analogue_gain_code_ registers, the associated value in the on semiconductor gain model can be read from the associated _gain register. in cases where there is more than one possible mapping, the 2x ga in stage is enabled to provide the mapping with the lowest noise. when the on semiconductor gain model is in use and values have been written to the gain_ registers, data read from the associated analog ue_gain_code_ register is undefined. the reason for this is that many of the gain codes available in the on semiconductor gain model have no corr esponding value in the smia gain model. the result is that the two gain models can be used interchangeably, but having written gains through one set of registers, those gains should be read back through the same set of registers. gain = analogue_gain_m0 x analogue_gain_code analogue_gain_c1 ------------------- --------------------- --------------------- --------------------- ------------------- - analogue_gain_code_ 8 --------------------- --------------------- ----------------- --------------- = gain _gain[8] 1 + ?? _gain[7] 1 + ?? ? _gain[6:0] 32 --------------- ----------------- -------------- - ? =
mt9d015: 1/5-inch 2 mp cmos digital image sensor features mt9d015_ds rev. m pub. 4/15 en 52 ?semiconductor components industries, llc,2015. minimum gain and gain table to make the sensor reach saturation status in high light condition, the gain value applied to this part must larger than 1.375x. in other words, the 1.375x is the minimum gain. table 16: gain table smia gain (r0x0204) global gain (r0x305e) gain 0x0008 0x1020 1 0x0009 0x1024 1.125 0x000a 0x1028 1.25 0x000b 0x102c 1.375 0x000c 0x1030 1.5 0x000d 0x1034 1.625 0x000e 0x1038 1.75 0x000f 0x103c 1.875 0x0010 0x10a0 2 0x0011 0x10a2 2.125 0x0012 0x10a4 2.25 0x0013 0x10a6 2.375 0x0014 0x10a8 2.5 0x0015 0x10aa 2.625 0x0016 0x10ac 2.75 0x0017 0x10ae 2.875 0x0018 0x10b0 3 0x0019 0x10b2 3.125 0x001a 0x10b4 3.25 0x001b 0x10b6 3.375 0x001c 0x10b8 3.5 0x001d 0x10ba 3.625 0x001e 0x10bc 3.75 0x001f 0x10be 3.875 0x0020 0x10c0 4 0x0021 0x10c2 4.125 0x0022 0x10c4 4.25 0x0023 0x10c6 4.375 0x0024 0x10c8 4.5 0x0025 0x10ca 4.625 0x0026 0x10cc 4.75 0x0027 0x10ce 4.875 0x0028 0x10d0 5 0x0029 0x10d2 5.125 0x002a 0x10d4 5.25 0x002b 0x10d6 5.375 0x002c 0x10d8 5.5 0x002d 0x10da 5.625 0x002e 0x10dc 5.75 0x002f 0x10de 5.875 0x0030 0x10e0 6
mt9d015: 1/5-inch 2 mp cmos digital image sensor features mt9d015_ds rev. m pub. 4/15 en 53 ?semiconductor components industries, llc,2015. 0x0031 0x10e2 6.125 0x0032 0x10e4 6.25 0x0033 0x10e6 6.375 0x0034 0x10e8 6.5 0x0035 0x10ea 6.625 0x0036 0x10ec 6.75 0x0037 0x10ee 6.875 0x0038 0x10f0 7 0x0039 0x10f2 7.125 0x003a 0x10f4 7.25 0x003b 0x10f6 7.375 0x003c 0x10f8 7.5 0x003d 0x10fa 7.625 0x003e 0x10fc 7.75 0x003f 0x10fe 7.875 0x0040 0x11c0 8 0x0041 0x11c1 8.125 0x0042 0x11c2 8.25 0x0043 0x11c3 8.375 0x0044 0x11c4 8.5 0x0045 0x11c5 8.625 0x0046 0x11c6 8.75 0x0047 0x11c7 8.875 0x0048 0x11c8 9 0x0049 0x11c9 9.125 0x004a 0x11ca 9.25 0x004b 0x11cb 9.375 0x004c 0x11cc 9.5 0x004d 0x11cd 9.625 0x004e 0x11ce 9.75 0x004f 0x11cf 9.875 0x0050 0x11d0 10 0x0051 0x11d1 10.125 0x0052 0x11d2 10.25 0x0053 0x11d3 10.375 0x0054 0x11d4 10.5 0x0055 0x11d5 10.625 0x0056 0x11d6 10.75 0x0057 0x11d7 10.875 0x0058 0x11d8 11 0x0059 0x11d9 11.125 0x005a 0x11da 11.25 0x005b 0x11db 11.375 0x005c 0x11dc 11.5 0x005d 0x11dd 11.625 table 16: gain table (continued) smia gain (r0x0204) global gain (r0x305e) gain
mt9d015: 1/5-inch 2 mp cmos digital image sensor features mt9d015_ds rev. m pub. 4/15 en 54 ?semiconductor components industries, llc,2015. notes: 1. 1-1.25 gains have been grayed out. customer s should not use less than x1.375 gain to avoid un-sat- uration issue. 2. the gain range 1-7.875 used analog gain only. the range 8 - 15.875 used 2x digital gain. when r0x0204[6]= r0x305e[8]=1, 2x digital gain is enabled. 0x005e 0x11de 11.75 0x005f 0x11df 11.875 0x0060 0x11e0 12 0x0061 0x11e1 12.125 0x0062 0x11e2 12.25 0x0063 0x11e3 12.375 0x0064 0x11e4 12.5 0x0065 0x11e5 12.625 0x0066 0x11e6 12.75 0x0067 0x11e7 12.875 0x0068 0x11e8 13 0x0069 0x11e9 13.125 0x006a 0x11ea 13.25 0x006b 0x11eb 13.375 0x006c 0x11ec 13.5 0x006d 0x11ed 13.625 0x006e 0x11ee 13.75 0x006f 0x11ef 13.875 0x0070 0x11f0 14 0x0071 0x11f1 14.125 0x0072 0x11f2 14.25 0x0073 0x11f3 14.375 0x0074 0x11f4 14.5 0x0075 0x11f5 14.625 0x0076 0x11f6 14.75 0x0077 0x11f7 14.875 0x0078 0x11f8 15 0x0079 0x11f9 15.125 0x007a 0x11fa 15.25 0x007b 0x11fb 15.375 0x007c 0x11fc 15.5 0x007d 0x11fd 15.625 0x007e 0x11fe 15.75 0x007f 0x11ff 15.875 table 16: gain table (continued) smia gain (r0x0204) global gain (r0x305e) gain
mt9d015: 1/5-inch 2 mp cmos digital image sensor sensor core digital data path mt9d015_ds rev. m pub. 4/15 en 55 ?semiconductor components industries, llc,2015. sensor core digital data path test patterns the mt9d015 supports a number of test pa tterns to facilitate system debug. test patterns are enabled using test_pattern_mode (r0x0600?1). the test patterns are listed in table 17. test patterns 0?3 replace pixel data in the output image (the embedded data rows are still present). test pattern 4 replaces all data in the output image (the embedded data rows are omitted and test pattern data replaces the pixel data). for all of the test patterns, the mt9d015 registers must be set appropriately to control the frame rate and output timing. these include: ?all clock divisors ? x_addr_start ? x_addr_end ? y_addr_start ? y_addr_end ? frame_length_lines ?line_length_pck ?x_output_size ? y_output_size the mt9d015 will disable digital corrections automatically when test patterns are acti- vated. the test cursor is now added to the end of the data path. solid color test pattern in this mode, all pixel data is replaced by fixed bayer pattern test data. the intensity of each pixel is set by its associated test data register (test_data_red, test_data_greenr, test_data_blue, test_data_greenb). table 17: test patterns test_pattern_mode description 0 normal operation: no test pattern 1 solid color 2 100% color bars 3fade-to-gray color bars 4 pn9 link integrity pattern
mt9d015: 1/5-inch 2 mp cmos digital image sensor sensor core digital data path mt9d015_ds rev. m pub. 4/15 en 56 ?semiconductor components industries, llc,2015. 100 percent color bars test pattern in this test pattern, shown in figure 23 on page 56, all pixel data is replaced by a bayer version of an 8-color, color-bar chart (white, yellow, cyan, green, magenta, red, blue, and black). each bar is 200 pixels wide and occupies the full height of the output image. each color component of each bar is set to either ?0? (fully off ) or 0x3ff (fully on for 10-bit data). the pattern repeats after 8 * 200 = 1600 pixels. the image size is set by x_ad- dr_start, x_addr_end, y_addr_s tart, y_addr_end and may be affected by the setting of x_output_size, y_output_size. the color-bar pa ttern starts at the column identified by x_addr_start. the number of colors that ar e visible in the output is dependent upon x_addr_end ? x_addr_start and the setting of x_output_size. the width of each color-bar is fixed at 200 pixels. the effect of setting horizontal_mirror in conjunction with this test pattern is that the order in which the colors are generated is reve rsed. the black bar appears at the left side of the output image. any pattern repeat occu rs at the right side of the output image regardless of the setting of horizontal_mirror. the state of vertical_flip has no effect on this test pattern. the effect of subsampling and sc aling of this test pattern is undefined. figure 23: 100 percent color bars test pattern horizontal mirror = 0 horizontal mirror = 1
mt9d015: 1/5-inch 2 mp cmos digital image sensor sensor core digital data path mt9d015_ds rev. m pub. 4/15 en 57 ?semiconductor components industries, llc,2015. fade-to-gray color bars test pattern in this test pattern, shown in figure 24 on page 58, all pixel data is replaced by a bayer version of an 8-color, color-bar chart (white, yellow, cyan, green, magenta, red, blue, and black). each bar is 200 pixels wide and occu pies 1024 rows of th e output image. each color bar fades vertically from full intensit y at the top of the image to 50 percent inten- sity (mid-gray) on the 1024th row. each color ba r is divided into a left and a right half, in which the left half fades smoothly and the right half fades in quantized steps every 8 pixels for a given color. due to the bayer patte rn of the colors this means that the level changes every 16 rows. the pattern repeats horizontally after 8 * 200 = 1600 pixels and vertically after 1024 rows (usi ng 10-bit data, the fade-to-gray pattern goes from 100 to 50 percent or from 0 to 50 percent for each color component, so only half of the 2 10 states of the 10-bit data are used. however, to get all of the gray levels, each state must be held for two rows, hence the vertical size of 2 10 / 2 * 2 = 1024). the image size is set by x_ad- dr_start, x_addr_end, y_addr_start, and y_addr_end and may be affected by the setting of x_output_size and y_output_size. the color- bar pattern starts at the column identi- fied by x_addr_start. the number of colors that are visible in the output is dependent upon x_addr_end ? x_addr_start and the setti ng of x_output_size. the width of each color-bar is fixed at 200 pixels. the effect of setting horizontal_mirror or vertical_flip in conjunction with this test pattern is that the order in which the colors are generated is reversed. the black bar appears at the left side of the output image. any pattern repeat occurs at the right side of the output image regardless of the setting of horizontal_mirror. the effect of subsampling and sc aling of this test pattern is undefined.
mt9d015: 1/5-inch 2 mp cmos digital image sensor sensor core digital data path mt9d015_ds rev. m pub. 4/15 en 58 ?semiconductor components industries, llc,2015. figure 24: fade-to-gray color bars test pattern pn9 link integrity pattern this test pattern provides a 512-bit pseudo-ran dom test sequence to test the integrity of the serial pixel data output stream. the polynomial x 9 + x 5 + 1 is used. the polynomial is initialized to 0x1ff at the start of each frame. when this test pattern is enabled: ? the embedded data rows are disabled, an d the value of frame_ format_decriptor_1 changes from 0x1002 to 0x1000 to indicate that no rows of embedded data are present. ? the whole output frame, bounded by th e limits programmed in x_output_size and y_output_size, is fill ed with data from the pn9 sequence. ? the output data format is (effectively) fo rced into raw10 mode regardless of the state of the data_format register. this polynomial generates the following sequ ence of 10-bit values : 0x1ff, 0x378, 0x1a1, 0x336, 0x385, and so on. on the serial pixel data output, these values are streamed out sequentially without performing the raw10 packing to bytes that normally occurs on this interface. horizontal mirror = 0, vertical flip = 0 horizontal mirror = 0, vertical flip = 1 horizontal mirror = 1, vertical flip = 0 horizontal mirror = 1, vertical flip = 1
mt9d015: 1/5-inch 2 mp cmos digital image sensor sensor core digital data path mt9d015_ds rev. m pub. 4/15 en 59 ?semiconductor components industries, llc,2015. test cursors the mt9d015 supports one horizontal and one ve rtical cursor, allowing a ?cross hair? to be superimposed on the image or on test patterns 1?3. the position and width of each cursor ar e programmable in r0x31e8?0x31ee. each cursor can be inhibited by setting its width to ?0.? the programmed cursor position corresponds to an absolute row or column in the pixel array. for example, setting horizontal_cursor_ position to the same value as y_addr_start would result in a horizontal cursor being dr awn starting on the first row of the image. the cursors are opaque (they replace data fr om the imaged scene or test pattern). the color of each cursor is set by the values of the bayer components in the test_data_red, test_data_greenr, test_data_bl ue, and test_data_greenb registers. as a consequence, the cursors are the same color as test pattern 1 and are therefore invisible when test pattern 1 is selected. when vertical_cursor_position = 0x0fff, the vertical cursor operates in an automatic mode in which its position advances every fram e. in this mode the cursor starts at the column associated with x_addr_start = 0 and advances by a step-size of 8 columns each frame until it reaches the column associated with x_addr_start = 2040, after which it wraps (256 steps). note that the active pixel array is smaller than this, so in the last 56 steps the cursor will not be visible. the wi dth and color of the cursor in this automatic mode are controlled in the usual way. the effect of enabling the test cursors when the image_orientation register is non-zero is not defined by the smia specification. th e behavior of the mt9d015 is shown in figure 25 on page 60. in this figure the test cu rsors are shown as translucent for clarity. in practice, they are opaque (they overlay the imaged scene). the manner in which the test cursors are affected by the value of imag e_orientation can be understood from the following implementation details: ? the test cursors are inserted early in the da ta path, so that they correlate to rows and to columns of the physical pixel array (rat her than to x and to y coordinates of the output image). ? the drawing of a cursor starts when the pixel array row or column address matches the value of the associated cursor_position re gister. as a result, the cursor start posi- tion remains fixed relative to the rows and columns of the pixel array for all settings of image_orientation. ? the cursor generation continues until the appropriate cursor_width pixels have been drawn. the cursor width is generated from the start position and proceeds in the direction of pixel array readout. as a result , each cursor is reflected about an axis corresponding to its start position when th e appropriate bit is set in the image_orien- tation register.
mt9d015: 1/5-inch 2 mp cmos digital image sensor sensor core digital data path mt9d015_ds rev. m pub. 4/15 en 60 ?semiconductor components industries, llc,2015. figure 25: test cursor behavior when image_orientation digital gain integer digital gains in the range 1?7 can be programmed. a digital gain of ?0? sets all pixel values to ?0? (the pixel data will simply represent the value applied by the pedestal block). pedestal this block adds the value from r0x0008-9 (d ata_pedestal_) to the incoming pixel value. the data_pedestal register is read-only by default but can be made read/write by clearing the lock_reg bit in r0x301a?b. the only way to disable the effect of the pedestal is to set it to ?0.? readout direction vertical cursor start horizontal cursor start horizontal mirror = 0, vertical flip = 0 vertical cursor start horizontal cursor start horizontal mirror = 0, vertical flip = 1 vertical cursor start horizontal cursor start horizontal mirror = 1, vertical flip = 0 vertical cursor start horizontal cursor start horizontal mirror = 1, vertical flip = 1 readout direction readout direction readout direction
mt9d015: 1/5-inch 2 mp cmos digital image sensor digital data path mt9d015_ds rev. m pub. 4/15 en 61 ?semiconductor components industries, llc,2015. digital data path the digital data path after the sensor core is shown in figure 26. figure 26: data path scaler output buffer limiter compression registers embedded data serial pixel data interface interface with sensor_core
mt9d015: 1/5-inch 2 mp cmos digital image sensor timing specifications mt9d015_ds rev. m pub. 4/15 en 62 ?semiconductor components industries, llc,2015. timing specifications power-up specifications the digital and analog supply voltages can be powered up in any order. however, on semiconductor recommends the following power-up sequence to minimize current consumption. the power-up sequence corresponds to the requirements described in section 3.2 of the smia functional specification. power-up sequence the recommended power-up sequence for the mt9d015 is shown in figure 27 and table 18 on page 63. the available power supplies?v dd , v dd _pll, v aa , v aa _pix?can be turned on at any point or have the sepa ration specified below for reducing current consumption during power-up sequence. 1. turn on the v dd power supply. 2. after 0?500ms, turn on v dd _pll and v aa /v aa _pix power supplies. 3. after the last power supply is stable, enable extclk. 4. after extclk is stable, asse rt reset_bar for at least 1ms. 5. wait 1200 extclks for internal initialization into soft standby. 6. configure pll, output, and image settings to desired values. 7. wait 16000 extclks for the pll to lock before streaming state is reached (enforced in hardware). 8. set mode_select = 1 (r0x0100) to start streaming. figure 27: power-up sequence v dd v dd _pll v aa , v aa _pix extclk reset_bar internal init hard reset software standby start i 2 c access pll lock streaming t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 software standby program otpm v pp 2.5v 8.5v
mt9d015: 1/5-inch 2 mp cmos digital image sensor timing specifications mt9d015_ds rev. m pub. 4/15 en 63 ?semiconductor components industries, llc,2015. power-down specification the digital and analog supply voltages can be powered down in any order. however, on semiconductor recommends the following power-down sequence to minimize current consumption. the power-down sequence corresponds to the requirements described in section 3.2 of the smia functional specification. power-down sequence the recommended power-down sequence for the mt9d015 is shown in figure 28 and in table 19 on page 64. the available power supplies?v dd , v dd _pll, v aa , v aa _pix?can be turned off at any point or have the sepa ration specified below for reducing current consumption during power-down sequence. 1. disable streaming if output is active by setting mode_select = 0 (r0x0100). 2. the soft standby state is reached after the current row or frame, depending on config- uration, has ended. 3. assert hard reset by setting rese t_bar to a logic ?0? at least 1ms. 4. stop extclk; drive this pin to logic ?0.? 5. turn off the v aa /v aa _pix and v dd _pll power supplies. 6. after 0 ? 500ms, turn off v dd and power supply. table 18: power-up sequence definition symbol min typ max unit v dd to v dd _pll time t 1 0 C 500 ms v dd to v aa /v aa _pix time t 2 0 C 500 ms active hard reset t 3 1CC ms internal initialization t 4 1200 C C extclks pll lock time t 5 16000 C C extclks soft standby t 6500C ms delay 1 t 7600C ms delay 2 t 8600C ms
mt9d015: 1/5-inch 2 mp cmos digital image sensor timing specifications mt9d015_ds rev. m pub. 4/15 en 64 ?semiconductor components industries, llc,2015. figure 28: power-down sequence hard standby and hard reset the hard standby state is reached by the as sertion of the reset_bar pad (hard reset). register values are not retained by this action, and will be returned to their default values once hard reset is completed. the minimum power consumption is achieved by the hard standby state. this operating mode complies with section 3.1 of the smia func- tional specification. soft standby and soft reset the mt9d015 can reduce power consumption by switching to the soft standby state when the output is not needed. register valu es are retained in the soft standby state. once this state is reached, soft reset can be optionally enabled to return all register values back to the default. the details of the sequence are shown in figure 29. soft standby 1. disable streaming if output is active by setting mode_select = 0 (r0x0100). 2. the soft standby state is reached after the current row or frame, depending on config- uration, has ended. soft reset 1. follow the soft standby sequence list. table 19: power-down sequence definition symbol min typ max unit hard reset t 1 1CCms v aa /v aa _pix to v dd time t 20C500ms v dd _pll to v dd time t 30C500ms v dd v dd _pll v aa , v aa _ pix extclk reset_bar turning off power supplies hard reset software standby streaming t 3 t 2 t 1
mt9d015_ds rev. m pub. 4/15 en 65 ?semiconductor components industries, llc,2015. mt9d015: 1/5-inch 2 mp cmos digital image sensor timing specifications 2. delay 1 frame time; set software_reset = 1 (r 0x0103) to start the internal initialization sequence. 3. after 700 extclks, the internal initializa tion sequence is comp leted and the current state returns to soft standby automatically. all registers, including software_reset, returns to their default values. figure 29: soft standby and soft reset extclk mode_select r0x0100 software_reset r0x0103 logic 1 logic 0 streaming soft standby soft reset soft standby next row/frame logic 0 logic 1 logic 0 1200 extclks delay 1 frame
mt9d015_ds rev. m pub. 4/15 en 66 ?semiconductor components industries, llc,2015. mt9d015: 1/5-inch 2 mp cmos digital image sensor electrical specifications electrical specifications extclk the electrical characteristics of the extclk input are shown in table . the extclk input supports an ac-coupled sine-wave input clock or a dc-coupled square-wave input clock. two-wire serial register interface table 21 describes the i/o levels, i/o current and pin capacitance for two-wire serial interface. table 22 describes timing specification for two-wire serial interface. figure 30: ?definition of timing for two-wire se rial interface,? on page 67 shows timing parameters definition. table 20: electrical characteristics (extclk) definition condition symbol min typ max unit input clock frequency f extclk 61627 mhz input clock period t extclk 166.7 62.5 37 ns input clock minimum voltage swing (ac coupled sine wave) v in _ac 0.5 1 1.2 v (pk-pk) input clock duty cycle 45 50 55 % input clock jitter cycle-to-cycle t jitter 545 600 ps pll vco lock time ( at 16 mhz extclk) t lock 3200 ext clk cycles input pad capacitance c in 3.75 pf input high leakage current v in =vvd i ih -10 - 10 ? a input low leakage current v in =d gnd i il -10 - 10 ? a input high voltage(dc coupled) v ih 0.7 x vdig - 2.9 v input low voltage (dc coupled) v ll -0.3 - 0.3 x v dd v table 21: two-wire serial interf ace electrical characteristics v dd = 1.7-1.9v; v aa = 2.4 -3.1v; environment temperature = -30c to 50c symbol definition condition min max unit v ih input high voltage 0.7v dd 2.9 v vil input low voltage -0.3 0.3v dd v v ol output low voltage at 3ma sink current 00.4v i ol output low current v ol =0.4v 3 - ma ii input current each i/o pin no pull-up resistor; v in = v dd or d gnd -10 +10 ? a ci capacitance for each i/o pin - 6 pf c load load capacitance n/a n/a pf
mt9d015_ds rev. m pub. 4/15 en 67 ?semiconductor components industries, llc,2015. mt9d015: 1/5-inch 2 mp cmos digital image sensor electrical specifications note: max t sdh could be 0.9 ? s but must be less than max of t sdv and t acv by a transition time. figure 30: definition of timing for two-wire serial interface table 22: two-wire serial interface timing specification v dd = 1.7-1.9v; v aa = 2.4 -3.1v; environment temperature = -30c to 50c symbol definition min max unit f sclk s clk frequency 0 400 khz t high s clk high period 0.6 - ? s t low s clk low period 1.3 - ? s t srts start setup time 0.6 - ? s t srth start hold time 0.6 - ? s t sds data setup time 100 - ns t sdh data hold time 0 note ? s t sdv data valid time - 0.9 ? s t acv data valid acknowledge time - 0.9 ? s t stps stop setup time 0.6 - ? s t buf bus free time between stop and start 1.3 - ? s tr s clk and s data rise time - 300 ns tf s clk and s data fall time - 300 ns sr s p s tsrts tstps tsds tsdh tsdv tsrth tf tr 9 th clock tbuf 1 st clock 9 th clock sdata sclk sdata sclk tl ow thigh // // // // // // tacv 70% 30% 70% 30% 70% 30% 70% 30% 70% 70% 70% 30% 30% 30% 30% 30% 70% 70% 70% 70% 70% 30%
mt9d015_ds rev. m pub. 4/15 en 68 ?semiconductor components industries, llc,2015. mt9d015: 1/5-inch 2 mp cmos digital image sensor electrical specifications serial pixel data interface the electrical characteristics of the serial pixel data interface (clk_p, clk_n, data_p, data_n are shown in table 23. table 23: electrical characteristics (serial ccp2 pixel data interface) v dd = 1.8v; v aa = 2.8v; v aa _pix = 2.8v; v dd _pll = 2.8v; ambient temperature definition symbol min typ max unit operating frequency 180 360 mhz fixed common mode voltage v cmf 0.8 0.9 1 v differential voltage swing v od 100 150 200 mv drive current range 0.83 1.5 2 ma drive current variation 15 % output impedance 40 140 ? output impedance mismatch 10 % clock duty cycle at 416 mhz 45 50 55 % rise time (20C80%) 300 400 ps fall time (20C80%) 300 400 ps differential skew 500 ps channel-to-channel slew 200 ps maximum data rate data/strobe mode data/clock mode 640 208 mb/s power supply rejection ratio (psrr) 0C100 mhz 30 db power supply rejection ratio (psrr) 100C1000 mhz 10 db table 24: electrical characteristics (serial mipi pixel data interface) v dd = 1.8v; v aa = 2.8v; v aa _pix = 2.8v; vv dd _pll = 2.8v; ambient temperature definition symbol min typ max unit high speed transmit differential voltage v od 140 270 mv high speed transmit static common-mode voltage v cmtx 150 250 mv v od mismatch when output is differential-1 or differential-0 dv od <14 mv high speed output high voltage mismatch dvcmtx 16 mv single ended output impedance z os 40 64 ? single ended output impedance mismatch dz os 10 ? 20C80% rise time t r250ps 20C80% fall time t f250ps output low level v ol 50 mv output high level v oh 1.3 v output impedance of low power parameter z olp 110 ? 15C85% rise time t rlp 25 ns 15C85% fall time t flp 25 ns
mt9d015_ds rev. m pub. 4/15 en 69 ?semiconductor components industries, llc,2015. mt9d015: 1/5-inch 2 mp cmos digital image sensor electrical specifications control interface the electrical characteristics of the cont rol interface (reset_bar, test, gpi0, gpi1, gpi2, and gpi3) are shown in table 25. power-on reset slew rate (c load = 5C20pf) dv/dtsr 235 mv/ns slew rate (c load = 20C70pf) dv/dstr 200 mv/ns power supply rejection rati o (psrr) 0C100 mhz 30 db power supply rejection ratio (psrr) 100C1000 mhz 10 db table 25: electrical characteristics definition condition symbol min typ max unit input high voltage v ih 0.7 x v dd 2.9 v input low voltage v il -0.3 0.3 x v dd v input leakage current no pull-up resistor; v in = v dd or d gnd i in 10 ? a input pad capacitance c in 6.5 pf table 26: power-on reset characteristics definition condition symbol min typ max unit v dd rising, crossing v trig _ rising ; internal reset being released t 171015 ? s v dd falling, crossing v trig _ falling ; internal reset active t 20.51 ? s minimum v dd spike width below v trig _ falling ; considered to be a reset when por cell output is high t 30.5 ? s minimum v dd spike width below v trig _f alling ; considered to be a reset when por cell output is low t 41 ? s minimum v dd spike width above v trig _ rising ; considered to be a stable supply when por cell output is low while the por cell output is low, all v dd spikes above v trig _ rising less than t 5 must be ignored t 550ns v dd rising trigger voltage v trig _ rising 1.15 1.55 v v dd falling trigger voltage v trig _ falling 11.45v table 24: electrical characteristics (serial mipi pixel data interface) v dd = 1.8v; v aa = 2.8v; v aa _pix = 2.8v; vv dd _pll = 2.8v; ambient temperature definition symbol min typ max unit
mt9d015_ds rev. m pub. 4/15 en 70 ?semiconductor components industries, llc,2015. mt9d015: 1/5-inch 2 mp cmos digital image sensor electrical specifications figure 31: internal power-on reset v dd por cell output t 1 t 0 burst< t 4 burst > t 3 burst< t 5 burst> t 5 v trig _ rising v trig _ falling 10% t 2 t 1 90%
mt9d015_ds rev. m pub. 4/15 en 71 ?semiconductor components industries, llc,2015. mt9d015: 1/5-inch 2 mp cmos digital image sensor electrical specifications operating voltages v aa and v aa _pix must be at the same potential for correct operation of the mt9d015. table 27: dc electrical defi nitions and characteristics setup conditions: tj = 25c; dark lighting conditions definition condition symbol min typ max unit core digital voltage v dd 1.7 1.8 1.9 v analog voltage v aa 2.4 2.8 2.9 v pixel supply voltage v aa _pix 2.4 2.8 2.9 v pll supply voltage v dd _pll 2.4 2.8 2.9 v digital operating current 1600x1200 at 30 fps idig 10 50 71 ma analog operating current iana 25 65 80 ma digital operating current 1600x1200 at 15fps idig 25 30 ma analog operating current iana 52 58 ma digital operating current 1280 x720 at30 fps idig 48 55 ma full field of view analog operating current iana 65 73 ma digital operating current 640x480 at 30 fps idig 24 30 ma analog operating current iana 40 45 ma digital operating current 320x240 at 120 fps idig 30 35 ma analog operating current iana 49 55 ma hard standby analog 10 ua digital 15 ua soft standby (clock off) analog 20 275 ua digital 30 300 ua soft standby (clock on 6 mhz) analog 20 275 ua digital 50 500 ua soft standby (clock on 27 mhz) analog 20 275 ua digital 1 3 ma
mt9d015_ds rev. m pub. 4/15 en 72 ?semiconductor components industries, llc,2015. mt9d015: 1/5-inch 2 mp cmos digital image sensor chief ray angle absolute maximum ratings caution stresses greater than those listed in table 28 may cause permanent damage to the device. exposure to absolute maximum rating conditions for extended periods may affect reliabil- ity. note: this is a stress rating only, and functional oper ation of the device at these or any other conditions above those indicated in the operational sect ions of this specific ation is not implied. chief ray angle table 28: absolute maximum values definition condition symbol min max unit core digital voltage v dd _ max -0.3 2.2 v analog voltage v aa _ max -0.3 3.2 v pixel supply voltage v aa _pix_ max -0.3 3.2 v pll supply voltage v dd _pll_ max -0.3 3.2 v input high voltage v ih _ max 0.7 x v dd v aa + 0.3 v input low voltage v ih _ max -0.3 0.3 x v dd v operating temperature measure at junction t op -30 70 c storage temperature t stg -40 125 c figure 32: chief ray angle cra vs. image height plot image height cra () (%) (mm) 000 5 0.088 2.14 10 0.175 4.21 15 0.263 6.25 20 0.350 8.27 25 0.438 10.27 30 0.525 12.24 35 0.613 14.16 40 0.700 16.00 45 0.788 17.74 50 0.875 19.36 55 0.963 20.83 60 1.050 22.12 65 1.138 23.23 70 1.225 24.13 75 1.313 24.81 80 1.400 25.26 85 1.488 25.47 90 1.575 25.42 95 1.663 25.07 100 1.750 24.40 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 0 102030405060708090100110 cra (deg) image height (%)
mt9d015_ds rev. m pub. 4/15 en 73 ?semiconductor components industries, llc,2015. mt9d015: 1/5-inch 2 mp cmos digital image sensor smia and mipi specification reference smia and mipi specification reference the sensor design and this documentation is based on the following reference docu- ments: ? smia specifications: ? functional specification: smia 1.0 part 1: functional specificat ion (version 1.0 dated 30 june 2004) smia 1.0 part 1: functional specification ecr0001 (version 1.0 dated 11 feb 2005) ? electrical specification: smia 1.0 part 2: ccp2 specification (version 1.0 dated 30 june 2004) smia 1.0 part 2: ccp2 specification ecr0001 (version 1.0 dated 11 feb 2005) ? mipi specifications: ? mipi alliance standard for csi-2 version 1.0 ? mipi alliance standard for d-phy version 1.0
mt9d015_ds rev. m pub. 4/15 en 74 ?semiconductor components industries, llc,2015. mt9d015: 1/5-inch 2 mp cmos digital image sensor revision history revision history rev. m. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4/15/15 ? updated ?ordering information? on page 2 rev. l . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3/26/15 ? updated to on semiconductor template ? removed confidential marking rev. k . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7/10/12 ? updated figure 27: ?power-up sequence,? on page 62 ? updated table 18, ?power-up sequence,? on page 63 rev. j. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1/24/12 ? updated table 27, ?dc electrical defi nitions and characteristics,? on page 71 rev. h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9/26/11 ? updated ?minimum gain and gain table? on page 52 ? updated table 16, ?gain table,? on page 52 ? updated table 20, ?electrical characteristics (extclk),? on page 66 ? updated ?two-wire serial register interface? on page 66 ? updated table 26, ?power-on reset characteristics,? on page 69 rev.g . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7/15/11 ? updated ?features? on page 1 ? updated table 1, ?key performance parameters,? on page 1 ? updated note 7 and added note 8 in figure 3: ?typical configur ation (connection) ? serial output mode,? on page 8 and in figure 4: ?typical configuration (connection) ? mipi mode,? on page 9 ? updated table 6, ?embedded data,? on page 19 ? updated table 11, ?streaming/standby,? on page 36 ? updated ?profile 0 behavior? on page 37 ? added ?one-time programmable memory (otpm)? on page 41 ? added ?full resolution frame structure with embedded data? on page 43 ? added note to ?frame rate control? on page 48 ?added ?minimum row time? on page48 ? added ?minimum frame time? on page 48 ? added ?fine integration time limits? on page 49 ? added ?minimum gain and gain table? on page 52 ? updated table 23, ?electrical characteristics (serial ccp2 pixel data interface),? on page 68 ? updated table 24, ?electrical characteristics (serial mipi pixel data interface),? on page 68 ? updated figure 31: ?internal power-on reset,? on page 70 ? updated table 27, ?dc electrical defi nitions and characteristics,? on page 71 ? updated ?smia and mipi specification reference? on page 73 rev. f . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1/14/11 ? added information for mipi functionality ? added ?chief ray angle? on page 72
on semiconductor and the on logo are registered trademarks of semiconductor components industries, llc (scillc) or its subsidia ries in the united states and/or other countries. scillc owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. a listing of scillcs pr oduct/patent coverage may be accessed at www.onsemi.com/site/pdf/ patent-marking.pdf. scillc reserves the right to make changes without further noti ce to any products herein. scillc makes no warranty, representat ion or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaim s any and all liability, including without limitation special, consequential or incidental damages. typical parameters which may be provided in scillc data shee ts and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including typicals must be validated for each customer a pplication by customers technical experts. scillc does not convey any license under its patent rights nor the rights of others. sc illc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in whic h the failure of the scillc prod uct could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such uninte nded or unauthorized applicatio n, buyer shall indemnify and hol d scillc and its officers, employ ees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly o r indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to a ll applicable copyright laws and is not for resale in any manner. mt9d015: 1/5-inch 2 mp cmos digital image sensor revision history mt9d015_ds rev. m pub. 4/15 en 75 ?semiconductor components industries, llc,2015 . rev. e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12/9/10 ? added maximum values for digital operating current and analog operating current in table 22, ?dc electrical definitions and characteristics,? on page 62 ? updated figure 28: ?power-down sequence,? on page 64 rev. d, production . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11/18/10 ? updated to production ? applied updated aptina template ? updated table 1, ?key performance parameters,? on page 1 rev. c, preliminary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10/8/10 ? updated table 20, ?electrical characteristics (extclk),? on page 66 ? updated table 21, ?two-wire serial register interface electrical characteristics,? on page 65 ? updated table 23, ?electrical characteristics (serial ccp2 pixel data interface),? on page 68 ? updated table 25, ?electrical characteristics,? on page 69 ? updated table 26, ?power-on reset characteristics,? on page 69 ? updated table 22, ?dc electrical defi nitions and characteristics,? on page 62 ? updated table 28, ?absolute maximum values,? on page 72 rev. b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8/13/10 ? updated ?effect of ccp2 class on legal range of output sizes/frame rate? on page 30 ? updated figure 13: ?mt9d015 system states,? on page 34 ? updated table 9, ?pll in system states,? on page 35 ? updated ?power-on reset sequence? on page 35 ? updated ?general purpose inputs? on page 36 ? updated figure 14: ?mt9d015 smia profile 1/2 clocking structure,? on page 38 ? updated figure 15: ?mt9d015 smia profile 0 clocking structure,? on page 39 ? updated equation 12 on page 49 ? updated ?power-up sequence? on page 62 ? updated table 18, ?power-up sequence,? on page 63 ? updated figure 29: ?soft standby and soft reset,? on page 65 ? deleted note from table 16, ?electrical characteristics (extclk),? on page 59 rev. a, advance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8/10/10 ?initial release

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